Vertical Non-Volatile Memory Barrier Design
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Solution Overview
Problem
In vertical non-volatile memory, dopant diffusion between adjacent source, drain, and channel regions during thermal treatment affects the reliability and size consistency of these regions, reducing memory reliability as component sizes shrink.
Innovation Solution
Incorporating thin film barriers, such as oxide, nitride, or oxynitride, between semiconductor layers to control junction locations and prevent dopant diffusion, while using a stacked structure with specific conductive states and dielectric layers for improved memory performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If component size is reduced to increase memory density, then more memory can be stored in limited area, but dopant diffusion occurs during thermal treatment affecting junction location precision
Solution Approach 1:
A barrier layer is introduced as an intermediary between the source/drain regions and the channel region. This barrier layer physically blocks dopant diffusion during thermal treatment, preventing junction location shifts while maintaining the scaled-down component dimensions needed for high memory density
Solution Approach 2:
The barrier layer is formed in advance before dopant implantation and thermal treatment steps. This preliminary structure prevents dopant diffusion proactively, countering the harmful effect before it can occur during subsequent processing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The barriers effectively prevent improper dopant diffusion, allowing for accurate control of junction locations and enhanced reliability and ease of manufacturing in vertical non-volatile memory devices.
Implementation Method 1
the first barrier is disposed between the first and the second semiconductor layers and the second barrier is disposed between the second and the third semiconductor layers
Data Source
AI summary
A manufacturing method of a vertical non-volatile memory is provided. A first semiconductor layer, a first barrier, a second semiconductor layer, a second barrier and a third semiconductor layer are formed on a substrate sequentially. The first and the third semiconductor layers have a first conductive state, while the second semiconductor layer has a second conductive state. Several strips of active stacked structures are formed by removing portions of the first, second and third semiconductor layers, and portions of the first and second barrier on the substrate. After forming a storage structure on the substrate, the storage structure is covered with a conductive layer filling spaces among the active stacked structures. A portion of the conductive layer is removed to form word lines across the active stacked structures.