Vertical Non-Volatile Memory Erase Voltage Control
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Solution Overview
Problem
Current memory devices face challenges in achieving high integration and improved electrical characteristics while maintaining reliability, particularly in their erase operations due to complex operation circuits and wiring structures.
Innovation Solution
A non-volatile memory device with a vertical structure is developed, featuring a memory cell region, a peripheral circuit region, and a substrate with a control logic circuit that outputs an erase enable signal to control the erase operation, including a substrate bias circuit that applies a substrate bias voltage and a row decoder to apply ground voltage to the ground select line, gradually increasing the voltage levels for effective erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory device size is reduced for high integration, then integration is improved, but operation circuits and wiring structures become complicated
Solution Approach 1:
The patent transitions from planar memory cell structures to vertical three-dimensional structures, stacking memory cells in the vertical direction. This dimensional change allows higher integration density without proportionally increasing the complexity of operation circuits and wiring, as the vertical stacking reduces the horizontal footprint while maintaining circuit functionality.
Solution Approach 2:
The patent implements shared read-disturb inhibit line structures that serve multiple functions: they inhibit read disturbances in some memory cells while simultaneously serving as bit lines for data transmission in other memory cells. This multi-functionality reduces the total number of separate wiring structures needed, addressing the complexity issue while maintaining high integration.
2Reliability
If erase voltage is applied directly to substrate, then erase operation is effective, but voltage control complexity increases
Solution Approach 1:
The patent applies a preliminary substrate bias voltage before applying the full erase voltage to the memory cell array. This preliminary biasing action prepares the substrate and memory cells for the subsequent erase operation, ensuring proper voltage distribution and reducing the risk of damage or malfunction when the high erase voltage is applied, thereby simplifying the overall voltage control sequence.
Solution Approach 2:
The patent segments the voltage control into distinct phases: applying substrate bias voltage to selected memory blocks, then applying erase voltage to specific memory cell arrays within those blocks. This segmentation allows precise control of erase operations in targeted regions without requiring complex voltage management across the entire memory device, simplifying the overall control architecture.
Data Source
AI summary
A non-volatile memory device includes a memory cell region including a first metal pad; a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad; a substrate in the memory cell region; a memory cell array in the memory cell region comprising a plurality of gate conductive layers stacked on the substrate and a plurality of pillars penetrating through the plurality of gate conductive layers and extending in a direction perpendicular to a top surface of the substrate, wherein at least one of the plurality of gate conductive layers is a ground select line; a control logic circuit in the peripheral circuit configured to output an erase enable signal for controlling an erase operation with respect to the memory cell array; a substrate bias circuit in the peripheral circuit configured to, in response to the erase enable signal, output a substrate bias voltage at a first target level to the substrate from a first time to a second time after the first time during a first delay period and, after the first delay period gradually increase a level of the substrate bias voltage to an erase voltage having a higher level than the first target level; and a row decoder in the peripheral circuit configured to apply a ground voltage to the ground select line based on control of the control logic circuit during the first delay period.