Vertical Non-Volatile Memory Device With Ferroelectric Layer
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Solution Overview
Problem
Vertical NAND flash memory devices face challenges with increased integration leading to interference between memory cells, charge loss, and reliability issues due to the thinness of insulating layers and high voltage requirements for write/erase operations, which affect operational reliability and integration.
Innovation Solution
A vertical non-volatile memory device design featuring alternately stacked insulating and conductive layers with a ferroelectric layer on the lateral surfaces of the conductive layers, allowing for a high degree of integration and reduced interference between memory cells, utilizing materials like fluorite-based or perovskite ferroelectric materials and semiconductor channel layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If insulating layers are made thinner to increase integration density, then manufacturing precision and device complexity improve, but reliability deteriorates due to charge loss and interference between memory cells
Solution Approach 1:
A ferroelectric layer is introduced as an intermediary between the channel layer and the control gate. This ferroelectric layer utilizes its spontaneous polarization to create an electric field that controls the channel, eliminating the need for high voltage and reducing charge loss through tunneling, thereby improving reliability while maintaining thin insulating layer structures for high integration density
Solution Approach 2:
The patent changes the electrical parameters by using the ferroelectric layer's polarization state (positive or negative) to control the memory cell state, replacing the traditional high-voltage threshold switching mechanism. This allows operation at lower voltages and reduces charge loss, enabling reliable operation with thinner insulating layers
2Manufacturing precision
If high voltage is applied for write/erase operations, then manufacturing precision improves, but reliability deteriorates due to increased charge loss and interference
Solution Approach 1:
The patent fundamentally changes the voltage parameter by utilizing the ferroelectric layer's ability to maintain polarization states at low voltages. The spontaneous polarization of the ferroelectric material creates sufficient electric field to control the channel without requiring high voltage, thereby eliminating charge loss through Fowler-Nordheim tunneling and improving operational stability
Solution Approach 2:
The patent replaces the traditional field-effect transistor voltage control mechanism with a ferroelectric polarization control mechanism. Instead of using high voltage to create an electric field for channel control, the ferroelectric layer's intrinsic polarization provides the necessary electric field at low voltages, substituting the high-voltage mechanical control with a materials-based field control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances integration density and reliability by minimizing charge loss and interference, enabling efficient memory operations with reduced voltage requirements and improved operational stability.
Implementation Method 1
when a gate voltage is applied to the plurality of conductive layers, the gate voltage may induce an electric field stronger than a coercive field in which ferroelectric polarization switching occurs in the ferroelectric layer
Data Source
AI summary
A vertical non-volatile memory device may include a plurality of insulating layers and a plurality of conductive layers alternately stacked on a surface of a substrate in a direction perpendicular to the surface of the substrate; a channel layer on the substrate, where the channel layer extends in the direction perpendicular to the surface of the substrate and the channel layer may be on lateral surfaces of the plurality of insulating layers and lateral surfaces of the plurality of conductive layers; and a ferroelectric layer between the channel layer and the lateral surfaces of the plurality of conductive layers.