Vertical Non-Volatile Memory Device With Metal Source Lines
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Solution Overview
Problem
Conventional planar structure non-volatile memory devices face limitations in reducing size and increasing integration and storage capacity due to design constraints.
Innovation Solution
A vertical non-volatile memory device is developed with metal source lines or metal silicide layers, featuring cell string units vertically arranged on a semiconductor substrate, impurity regions, conductive lines, and spacers to enhance storage capacity and integration, where the bottom surfaces of gate dielectric layers of selecting transistors are lower than the semiconductor substrate's top surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a planar structure non-volatile memory device is used, then the device structure is simple and easy to manufacture, but the storage capacity and integration are limited due to design rule constraints
Solution Approach 1:
The patent transitions from a planar (2D) structure to a vertical (3D) structure by arranging cell string units vertically on the semiconductor substrate. The channel layers extend vertically from the substrate surface, and gates are positioned at different heights, creating a three-dimensional memory architecture that increases storage capacity while maintaining manufacturability
2Device complexity
If a planar structure non-volatile memory device is used, then the device structure is simple, but the integration and storage capacity cannot be increased due to design rule limitations
Solution Approach 1:
The patent implements vertical stacking of multiple memory layers with channel layers, gates, and insulating layers arranged in three dimensions. This vertical integration allows multiple storage layers to be stacked above the substrate, significantly increasing integration density while managing device complexity through systematic layering
Solution Approach 2:
The patent embeds multiple functional layers within each other vertically - channel layers surround insulation pillars, gates are positioned around channel layers at different heights, and spacers are formed on sidewalls. This nested arrangement maximizes space utilization and integration within the vertical dimension
3Ease of manufacture
If the bottom surfaces of gate dielectric layers are at the same level as the semiconductor substrate surface, then the fabrication process is simpler, but the storage capacity and integration are limited
Solution Approach 1:
The patent creates different surface levels for different regions: the bottom surfaces of gate dielectric layers of selecting transistors are positioned lower than the top surface of the semiconductor substrate in peripheral regions, while memory cell regions maintain their vertical structure. This localized depth variation optimizes both storage capacity and fabrication feasibility
Data Source
AI summary
Provided is a vertical non-volatile memory device having a metal source line. The vertical non-volatile memory device includes cell string units that are formed on first portions of a semiconductor substrate and are vertically arranged with respect to a surface of the semiconductor substrate, impurity regions formed on second portions of the semiconductor substrate between the cell string units, conductive lines formed on the impurity regions, and spacers that are formed on the sidewalls of the cell string units and insulate the conductive lines from the cells string units.