Vertical Non-Volatile Memory Multi-Level Cell Storage
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Solution Overview
Problem
Current vertical non-volatile memory devices face challenges in efficiently programming multi-level cells due to widened threshold voltage distributions caused by coupling between neighboring memory cells, especially as integration density increases, making it difficult to distinguish voltage distributions and store multiple bits of data effectively.
Innovation Solution
The proposed solution involves a vertical non-volatile memory device design with first and second charge storage structures on the outer and inner sidewalls of a channel, respectively, along with a back gate that further contributes to the threshold voltage, allowing for the easy realization of multi-level cell characteristics by sharing a channel with front gate electrodes, thereby enhancing data storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If integration density is increased to improve storage capacity, then more memory cells can be packed in a given area, but threshold voltage distribution widens due to coupling between neighboring cells, making it difficult to distinguish voltage levels for multi-level cell storage
Solution Approach 1:
The memory cell is divided into two independent charge storage structures (first and second charge storage structures) located on opposite sidewalls of the channel. Each charge storage structure can be independently programmed and read, allowing the memory system to overcome the threshold voltage distribution problem by using separate storage regions that do not suffer from the same coupling effects.
Solution Approach 2:
The patent transitions from a conventional single charge storage structure to a three-dimensional configuration with charge storage structures on both inner and outer sidewalls of the channel. This spatial arrangement in multiple dimensions allows for independent control and reduced interference between storage elements, enabling multi-level cell operation even at high integration densities.
2Device complexity
If conventional single charge storage structure is used, then device structure is simpler, but multi-level cell characteristics cannot be easily realized due to limited threshold voltage control
Solution Approach 1:
The patent combines two charge storage structures (first on outer sidewall, second on inner sidewall) into a single memory cell operation. This merging allows the cell to achieve multi-level cell characteristics by utilizing the combined threshold voltage contributions from both charge storage structures, enabling storage of multiple bits per cell without requiring completely separate cells for each storage function.
Solution Approach 2:
The dual charge storage structure design provides multi-functionality by enabling the same memory cell to operate in both single-level and multi-level modes. The first and second charge storage structures can be independently controlled to provide different threshold voltage levels, making the device adaptable to various storage requirements without changing the fundamental cell structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables improved data storage capabilities by allowing each memory cell to have characteristics of multi-level cells, potentially achieving quadruple, penta, or hexa level cell storage by utilizing the additional threshold voltage from the back gate, thus overcoming the limitations of integration density-induced voltage distribution widening.
Implementation Method 1
a first charge storage structure on an outer sidewall of the channel, a second charge storage structure on an inner sidewall of the channel
Implementation Method 2
first gate electrodes spaced apart from each other in the first direction on the substrate, each which surrounds the first charge storage structure, and a second gate electrode on an inner sidewall of the second charge storage structure
Data Source
AI summary
A vertical non-volatile memory device includes a channel on a substrate and extending in a first direction perpendicular to an upper surface of the substrate, a first charge storage structure on an outer sidewall of the channel, a second charge storage structure on an inner sidewall of the channel, first gate electrodes spaced apart from each other in the first direction on the substrate, each which surrounds the first charge storage structure, and a second gate electrode on an inner sidewall of the second charge storage structure.