Vertical Nonvolatile Memory Device With Segmented Via Areas
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Solution Overview
Problem
As information communication devices become more functional, nonvolatile memory devices face challenges in achieving high integration and large capacity while maintaining electrical characteristics, particularly due to the degradation of operation circuit complexity and wiring as memory cell sizes decrease.
Innovation Solution
A nonvolatile memory device with a vertical structure and a cell-over-peri (COP) architecture, featuring a first semiconductor layer with word-lines and bit-lines, a second semiconductor layer with address decoders and page buffer circuits, and a control circuit that manages these components, including a pad region with varying numbers of via areas to optimize signal and power delivery across the memory cell array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell sizes decrease to achieve high integration, then storage capacity increases, but electrical characteristics and operation circuit performance degrade
Solution Approach 1:
The patent transitions from a planar memory cell structure to a vertical three-dimensional structure. Memory cells are stacked vertically with word-lines extending in a first direction and bit-lines in a second perpendicular direction, creating a vertical channel structure that increases storage capacity without degrading electrical characteristics. This dimensional change allows high integration while maintaining reliable electrical performance.
2Quantity of substance
If memory cell sizes decrease to achieve high integration, then storage capacity increases, but operation circuit complexity increases
Solution Approach 1:
The memory device is divided into multiple semiconductor layers with distinct functional regions. The first semiconductor layer contains the memory cell array with vertical structures, while the second semiconductor layer contains address decoders and page buffer circuits. This segmentation allows independent optimization of each layer, reducing overall circuit complexity while achieving high storage capacity.
Solution Approach 2:
By stacking memory cells vertically in the third direction perpendicular to the word-line and bit-line directions, the patent achieves high integration without increasing the complexity of operation circuits in the planar directions. The vertical architecture separates storage functions from control functions across different layers.
3Ease of manufacture
If via areas are uniformly distributed, then manufacturing is simplified, but signal and power delivery efficiency decreases
Solution Approach 1:
The patent implements non-uniform via area distribution where via areas adjacent to the pad region have different sizes than those farther away. Vias closer to the pad region, which handle higher current and signal integrity requirements, are optimized with larger or differently configured areas. This local differentiation improves signal and power delivery efficiency without significantly complicating the manufacturing process.
Data Source
AI summary
A nonvolatile memory device includes a first semiconductor layer including an upper substrate in which word-lines extending in a first direction and bit-lines extending in a second direction are disposed and a memory cell array, a second semiconductor layer, a control circuit, and a pad region. The memory cell array includes a vertical structure on the upper substrate, and the vertical structure includes memory blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The vertical structure includes via areas in which one or more through-hole vias are provided, and the via areas are spaced apart in the second direction. The memory cell array includes mats corresponding to different bit-lines of the bit-lines. At least two of the mats include a different number of the via areas according to a distance from the pad region in the first direction.