Vertical Non-Volatile Memory Single-Crystal Channel Design
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Solution Overview
Problem
Existing semiconductor memory devices face challenges with reliability and integration due to crystalline defects, increased resistance, and tunnel oxide degradation in vertically oriented channel configurations, which affect device speed and power consumption.
Innovation Solution
The use of a single-crystal vertical channel and a thermal oxide tunnel layer, along with a charge trapping layer surrounding the control gate, enhances device reliability and endurance by reducing crystalline defects and improving insulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a poly-silicon vertical channel is used, then the device can be manufactured with conventional processes, but grain boundaries cause increased resistance and trap sites
Solution Approach 1:
The patent changes the material parameter from poly-silicon to single-crystal semiconductor material, fundamentally altering the crystal structure to eliminate grain boundaries while maintaining vertical channel architecture compatibility with existing manufacturing processes
Solution Approach 2:
The patent employs a composite structure combining single-crystal semiconductor material for the vertical channel with carefully engineered oxide layers (tunnel oxide, charge trapping layer, blocking oxide) to achieve both low resistance and high reliability
2Ease of manufacture
If CVD-formed tunnel oxide is used in the ONO charge-trapping layer, then the device can be formed with standard processes, but the tunnel oxide degrades quickly over time
Solution Approach 1:
The patent changes the formation method parameter from CVD to thermal oxidation, transforming the tunnel oxide creation process to achieve superior oxide quality with enhanced temporal stability and reduced degradation
Solution Approach 2:
The patent replaces the chemical vapor deposition process with a thermal oxidation process, substituting a chemically-driven formation mechanism with a thermally-driven one that produces more stable oxide structures
3Productivity
If vertically oriented channels with multiple gate layers are used, then device density is increased, but driver transistor size must scale with the number of layers leading to integration issues
Solution Approach 1:
The patent transitions from planar horizontal arrays to vertical channel architecture, utilizing the vertical dimension to increase device density while maintaining manageable driver transistor dimensions through the vertical stacking of memory cells
4Ease of manufacture
If conventional oxide layer is used to isolate select gates from vertical channel, then fabrication is simplified, but floating gate formation is difficult to achieve
Solution Approach 1:
The patent replaces the simple conventional oxide isolation layer with a composite multi-layer oxide structure including tunnel oxide, charge trapping layer, and blocking oxide, enabling precise floating gate formation while maintaining fabrication feasibility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces device resistance, increases speed, decreases power consumption, and provides greater flexibility in achieving desired device characteristics, leading to more reliable and efficient semiconductor memory devices.
Implementation Method 1
the tunnel oxide positioned between the charge trapping layer and the vertical channel is formed of a thermal oxide layer
Data Source
AI summary
In a semiconductor device, and a method of manufacturing thereof, the device includes a substrate of single-crystal semiconductor material extending in a horizontal direction and a plurality of interlayer dielectric layers on the substrate. A plurality of gate patterns are provided, each gate pattern being between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of single-crystal semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns, a gate insulating layer being between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel.