Vertical Non-Volatile Memory Device Fabrication
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Solution Overview
Problem
Conventional non-volatile memory devices with a horizontal structure face limitations in miniaturization, integration, and mass storage due to design rule reductions, restricting their ability to efficiently maintain memory data without an external power supply.
Innovation Solution
A method for fabricating a non-volatile memory device with a vertical structure, involving the alternately stacking of sacrificial and insulation films on a semiconductor substrate, forming channel layers, insulation pillars, and gate electrodes, and ion-injecting impurities to create conjunction regions, allowing for a more compact and efficient memory cell arrangement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If memory cells are arranged horizontally on a substrate, then the device structure is simple to manufacture, but the device cannot achieve miniaturization and high integration
Solution Approach 1:
The patent transitions from conventional two-dimensional horizontal arrangement of memory cells to a three-dimensional vertical structure. Multiple memory cells are stacked vertically along the thickness direction of the substrate, enabling miniaturization and high integration while maintaining manufacturability through standard semiconductor fabrication processes adapted for vertical geometry.
2Quantity of substance
If design rule is reduced to increase integration, then mass storage capability improves, but manufacturing precision requirements increase
Solution Approach 1:
By arranging memory cells in the vertical dimension rather than reducing horizontal dimensions, the patent achieves high integration without requiring proportional reduction in lateral design rules. This allows maintaining existing manufacturing precision capabilities while increasing the number of memory cells through vertical stacking.
Solution Approach 2:
The vertical structure divides the memory device into multiple discrete layers (substrate, insulation films, sacrificial films, channel layers, gate electrodes) that can be independently fabricated and controlled. This segmentation allows each layer to be optimized separately, reducing the cumulative impact of manufacturing variations.
3Area of moving object
If vertical structure is implemented for miniaturization, then integration density improves, but device complexity increases
Solution Approach 1:
The vertical memory structure is divided into distinct functional layers including substrate, alternating insulation and sacrificial films, channel layers, and gate electrodes. Each layer has a specific function and can be fabricated using standardized processes, managing complexity through modular design despite the three-dimensional architecture.
Solution Approach 2:
Insulation films and sacrificial films serve as intermediary layers that facilitate the formation of the vertical structure. These intermediary layers enable precise positioning and isolation of functional elements during fabrication, simplifying the overall manufacturing process despite the complex final geometry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The vertical structure enables enhanced miniaturization, integration, and mass storage capabilities, maintaining memory data without an external power supply, thereby overcoming the limitations of conventional devices.
Implementation Method 1
Impurities may be ion-injected into the plurality of second portions of the semiconductor substrate to form a plurality of common conjunction regions
Data Source
AI summary
A method of fabricating a non-volatile memory device according to an example embodiment may include etching a plurality of sacrificial films and insulation films to form a plurality of first openings that expose a plurality of first portions of a semiconductor substrate. A plurality of channel layers may be formed in the plurality of first openings so as to coat the plurality of first portions of the semiconductor substrate and side surfaces of the plurality of first openings. A plurality of insulation pillars may be formed on the plurality of channel layers so as to fill the plurality of first openings. The plurality of sacrificial films and insulation films may be further etched to form a plurality of second openings that expose a plurality of second portions of the semiconductor substrate. A plurality of side openings may be formed by removing the plurality of sacrificial films. A plurality of gate dielectric films may be formed on surfaces of the plurality of side openings. A plurality of gate electrodes may be formed on the plurality of gate dielectric films so as to fill the plurality of side openings.