Vertical OTP Memory Cell Layout for Higher Density DRAM
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Solution Overview
Problem
The scaling of DRAM devices faces challenges with increased memory cell density leading to disturbance errors and larger occupied areas due to planar transistors, necessitating advanced techniques to reduce size and improve performance.
Innovation Solution
Implementing vertical transistors in one-time-programmable (OTP) memory cells, where the anti-fuse storage structure is a MOSFET, and relocating part of the OTP memory cell array from the CMOS wafer to the array wafer, coupled through a hybrid bonding structure, reducing chip size and mitigating parasitic capacitance and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If planar transistors are used in memory cells, then the device structure is simple and easy to manufacture, but the occupied area increases and memory cell density decreases
Solution Approach 1:
The patent transitions from planar (2D) transistors to vertical (3D) transistors by changing the dimensional orientation of the transistor structure. The vertical transistor extends in the vertical direction with the channel forming a columnar structure, allowing current flow from source to drain vertically while the gate wraps around the channel. This dimensional change enables higher density without compromising manufacturability.
2Quantity of substance
If memory cell density is increased, then more memory can be stored in the same area, but disturbance errors increase
Solution Approach 1:
The patent segments the transistor structure into distinct vertical components (source, channel, drain) separated in the vertical direction, and isolates memory cells using interlayer insulating films between adjacent vertical transistors. This segmentation reduces parasitic coupling between adjacent cells while maintaining high density, thereby reducing disturbance errors.
3Device complexity
If OTP memory cell array is located entirely on CMOS wafer, then manufacturing process is simplified, but chip size increases and parasitic capacitance and resistance increase
Solution Approach 1:
The patent segments the OTP memory cell array into two parts: one part remains on the CMOS wafer and another part is formed on a separate array wafer. These two parts are subsequently bonded together through hybrid bonding. This segmentation reduces the chip size on each individual wafer and decreases parasitic capacitance and resistance by shortening interconnect lengths, while the bonding process integrates both parts into a functional whole.
Data Source
AI summary
The present disclosure describes memory systems and devices having vertical transistors in one-time-program (OTP) memory cells and fabrication methods thereof. An example semiconductor device includes a first array of memory cells including at least a first memory cell. The first memory cell includes a first vertical transistor and a storage structure coupled to the first vertical transistor in a first direction. The first array of memory cells is in a first area of a first semiconductor structure of the semiconductor device. The semiconductor device further includes a second array of memory cells including at least a second memory cell. The second memory cell includes a second vertical transistor in a second area of the first semiconductor structure. The second area is adjacent to the first area in a second direction perpendicular to the first direction.