Vertical Oxide Semiconductor Channel Structure for Low-Resistance Contacts
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Solution Overview
Problem
There is a need to reduce contact resistance between a channel with an oxide semiconductor material and a contact plug with metal in semiconductor devices, particularly in vertical channel transistors, to enhance electrical signal application and integration.
Innovation Solution
The semiconductor device incorporates a crystalline oxide semiconductor pattern that contacts the sidewall of the channel and the contact plug, forming a collective channel structure, which reduces contact resistance and increases carrier concentration, allowing for improved on-current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a vertical channel transistor with oxide semiconductor material is used to improve integration degree, then device integration is enhanced, but contact resistance between the channel and contact plug increases
Solution Approach 1:
The patent transitions from a conventional planar channel structure to a vertical channel structure, changing the spatial dimension of current flow. The channel extends vertically from the bit line upward, allowing the contact plug to access the channel from the top surface rather than requiring lateral contact, thus reducing contact resistance while maintaining high integration density.
Solution Approach 2:
The patent employs a composite material structure where the channel is formed using oxide semiconductor material (such as IGZO - indium gallium zinc oxide) combined with metal contact plugs. This composite approach leverages the beneficial properties of oxide semiconductors (high mobility, low off-state current) and metals (low contact resistance), resolving the contradiction between integration and contact quality.
2Productivity
If oxide semiconductor material is used in the channel to enable vertical channel structure, then device integration improves, but electrical signal application to the channel becomes difficult
Solution Approach 1:
The vertical channel structure allows electrical signals to be applied from the top surface of the substrate through the contact plug, rather than requiring complex lateral routing. This dimensional change simplifies signal application while maintaining high integration, as the contact plug can be directly connected to the channel top surface.
Solution Approach 2:
The contact plug acts as an intermediary element that bridges the external electrical signal source and the vertical channel. It provides a direct conductive path from the substrate surface to the channel, facilitating easy signal application without compromising the vertical structure or integration density.
3Reliability
If contact resistance between channel and contact plug is reduced, then electrical conductivity improves, but device complexity increases
Solution Approach 1:
By moving the contact point to the vertical dimension (top surface of the channel), the patent achieves low contact resistance without adding lateral complexity. The contact plug simply extends vertically to meet the channel, creating a straightforward structure that minimizes contact resistance while maintaining simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively lowers contact resistance and increases on-current by using a crystalline oxide semiconductor pattern to enhance the channel structure, facilitating better electrical conductivity and device performance.
Implementation Method 1
The oxide semiconductor pattern may include a crystalline oxide semiconductor material unlike the channel including an amorphous oxide semiconductor material
Data Source
AI summary
A semiconductor device includes a bit line on a substrate, a gate electrode on the bit line, a gate insulation pattern on a sidewall of the gate electrode, a channel that contacts an upper surface of the bit line and a sidewall of the gate insulation pattern, an oxide semiconductor pattern that contacts an upper sidewall of the channel, and a contact plug that contacts an upper surface of the channel and an upper surface of the oxide semiconductor pattern. The channel includes an amorphous oxide semiconductor material. The oxide semiconductor pattern includes a crystalline oxide semiconductor material.