Vertical Oxide Semiconductor Memory Channel for Higher Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices face challenges in increasing integration, operating speed, and yield due to reduced design rules, and transistors with vertical channels are needed to address these issues.
Innovation Solution
A semiconductor memory device is designed with a channel pattern comprising a first and second oxide semiconductor layer, where the second layer has a greater thickness and different gallium concentration than the first, and is integrated with word lines and a gate dielectric pattern to enhance electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors with vertical channels are introduced to increase integration and operating speed, then device performance improves, but device structure and fabrication process become more complex
Solution Approach 1:
The patent transitions from conventional planar horizontal channels to vertical channels extending in the thickness direction, utilizing the third dimension to increase device integration and operating speed while managing the associated structural complexity through systematic layer arrangement
Solution Approach 2:
The channel structure employs composite oxide semiconductor layers with different compositions (first oxide semiconductor layer with first composition, second oxide semiconductor layer with second composition) to optimize electrical properties while maintaining vertical channel architecture
2Reliability
If oxide semiconductor layers with different compositions and thicknesses are used to optimize electrical properties, then electron mobility and threshold voltage improve, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies different oxide semiconductor compositions locally within the channel structure - the first oxide semiconductor layer has a first composition optimized for certain electrical properties, while the second oxide semiconductor layer has a second composition optimized for other properties, allowing tailored electrical performance in different regions of the channel
Solution Approach 2:
The patent systematically varies key parameters including the thickness of each oxide semiconductor layer, the gallium concentration in each layer, and the composition ratios to optimize electrical characteristics such as electron mobility, subthreshold swing, and threshold voltage
Data Source
AI summary
Provided is a semiconductor memory device comprising a bit line extending in a first direction, a channel pattern on the bit line and including a first oxide semiconductor layer in contact with the bit line and a second oxide semiconductor layer on the first oxide semiconductor layer, wherein each of the first and second oxide semiconductor layers includes a horizontal part parallel to the bit line and first and second vertical parts that vertically protrude from the horizontal part, first and second word lines between the first and second vertical parts of the second oxide semiconductor layer and on the horizontal part of the second oxide semiconductor layer, and a gate dielectric pattern between the channel pattern and the first and second word lines. A thickness of the second oxide semiconductor layer is greater than that of the first oxide semiconductor layer.