Vertical Oxide TFT Channel Etching for Low-Leakage Memory Arrays
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Solution Overview
Problem
Conventional volatile memory cells experience sub-threshold leakage current, leading to charge loss and frequent refreshing, and existing etching methods leave residues that alter material properties and hinder high packing density in semiconductor structures.
Innovation Solution
The use of dry etching with a hydrogen bromide-based etchant, including gases like methane and nitrogen trifluoride, to form vertical thin film transistors with oxide semiconductor channels, achieving reduced leakage current and higher packing density without residue formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wet etching with oxalic acid is used to form channel regions, then the etching process is simple and easy to perform, but residue is formed on the structures which changes material properties and prevents high packing density
Solution Approach 1:
The patent changes the etching method from wet etching to dry etching, specifically using reactive ion etching (RIE) with a hydrogen bromide-based chemistry. This parameter change eliminates residue formation while achieving the required etching depth and profile control for high-density vertical transistor structures.
Solution Approach 2:
The patent replaces the chemical wet etching process with a physical-chemical dry etching process (reactive ion etching). This substitution uses plasma-generated radicals and ion bombardment to achieve clean etching without liquid residue, enabling higher packing density.
2Ease of manufacture
If conventional wet etchants are used for patterning, then the process is straightforward, but the residue left behind alters material properties of channel regions
Solution Approach 1:
The patent changes the etching medium from liquid wet etchant to gaseous dry etchant (hydrogen bromide-based plasma). This parameter change eliminates residue formation that alters material properties, while the controlled plasma chemistry maintains selectivity and etching quality.
Solution Approach 2:
The patent replaces wet chemical etching with dry plasma etching. The plasma process uses reactive species and ion energy to etch the oxide semiconductor material cleanly without leaving residual chemicals that would alter channel region material properties.
3Manufacturing precision
If vertical thin film transistors with oxide semiconductor channels are formed using dry etching with hydrogen bromide-based etchant, then packing density increases and residue formation is eliminated, but the process complexity increases
Solution Approach 1:
The patent employs reactive ion etching with hydrogen bromide-based chemistry, which provides anisotropic etching with vertical profiles and no residue. The process parameters (gas composition, power, pressure) are optimized to achieve the required etching depth and sidewall angle for high-density vertical structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in vertical thin film transistors with significantly reduced off-state leakage current and increased packing density, enabling more efficient memory cell design and operation with minimal material property alteration.
Implementation Method 1
exposing the channel material to a dry etchant comprising hydrogen bromide to pattern the channel material into channel regions
Implementation Method 2
exposing the channel material to a dry etchant comprising hydrogen bromide, methane, and nitrogen trifluoride
Data Source
AI summary
A method of forming a semiconductor structure comprises forming an array of vertical thin film transistors. Forming the array of vertical thin film transistors comprises forming a source region, forming a channel material comprising an oxide semiconductor material over the source region, exposing the channel material to a dry etchant comprising hydrogen bromide to pattern the channel material into channel regions of adjacent vertical thin film transistor structures, forming a gate dielectric material on sidewalls of the channel regions, forming a gate electrode material adjacent to the gate dielectric material, and forming a drain region over the channel regions. Related methods of forming semiconductor structures and an array of memory cells are also disclosed.