Vertical Oxide Semiconductor Transistor for BEOL DRAM Integration
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in increasing transistor density and reducing power consumption, particularly for DRAM access transistors, due to high temperature constraints in FEOL processing and the need for materials compatible with BEOL processing, while also requiring low gate-induced drain leakage and stable performance across a wide temperature range.
Innovation Solution
A vertical thin-film transistor structure is developed, compatible with BEOL processes, featuring a gate region extending perpendicular to the substrate, shared by two channel regions, and using materials like titanium nitride, tungsten, and oxide semiconductor materials, which reduces footprint, leakage, and allows for lower processing temperatures, enabling more efficient integration of DRAM cells in BEOL layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar transistor structures are used in FEOL processing, then manufacturing experience and process maturity are maintained, but transistor density increases are limited and processing temperatures are too high for BEOL integration
Solution Approach 1:
The patent transitions from planar (2D) transistor structures to vertical (3D) transistor structures by extending the channel region vertically from the substrate surface. This dimensional change increases transistor density without proportionally increasing footprint area and enables lower processing temperatures compatible with BEOL integration
Solution Approach 2:
The transistor structure is segmented into distinct functional regions including channel region, gate region, source region, and drain region, with the gate region wrapping around the channel region in a FinFET-like configuration. This segmentation allows independent optimization of each region's properties and processing conditions
2Productivity
If more circuit elements are integrated in the same IC size, then circuit element density increases, but manufacturing process complexity and material compatibility challenges increase
Solution Approach 1:
The vertical transistor structure serves multiple functions: it provides high-density integration, enables BEOL processing compatibility through low-temperature fabrication, achieves low gate-induced drain leakage through the wrapped gate configuration, and maintains performance stability across temperature ranges. This multi-functionality reduces the need for additional specialized structures
Solution Approach 2:
The transistor employs composite material structures including oxide semiconductor materials for the channel region, titanium nitride for the gate electrode, and various dielectric materials for isolation and insulation. These composite materials provide complementary properties that simultaneously address density, temperature, and performance requirements
3Temperature
If oxide semiconductor materials are used in the channel region, then processing temperatures are reduced for BEOL compatibility, but material selection and deposition process requirements become more stringent
Solution Approach 1:
The patent changes the material parameter from conventional silicon-based semiconductors to oxide semiconductor materials, which fundamentally alters the processing temperature regime from high-temperature FEOL to low-temperature BEOL compatible processes. This parameter change enables integration in later fabrication stages
Solution Approach 2:
A gate dielectric layer is introduced as an intermediary between the oxide semiconductor channel region and the gate electrode, providing proper electrical insulation and interface quality. This intermediary layer is critical for achieving low leakage while maintaining compatibility with low-temperature oxide semiconductor processing
4Object-generated harmful factors
If vertical transistor structures with wrapped gates are implemented, then gate-induced drain leakage is reduced and control is improved, but fabrication process steps and structural complexity increase
Solution Approach 1:
The gate region is extended from a planar configuration to a vertical wrapped configuration that surrounds the channel region on multiple sides. This 3D gate structure provides superior electrostatic control and reduces gate-induced drain leakage by eliminating the short-channel effects present in planar structures
Solution Approach 2:
The source and drain regions are merged with the channel region to form continuous vertical structures, with the gate region wrapping around these merged structures. This merging simplifies the overall fabrication process by reducing the number of discrete patterning steps required compared to fully separate structures
Data Source
AI summary
A semiconductor structure is provided. The semiconductor structure may include a transistor structure, the transistor structure may include a gate region arranged over an upper surface of a substrate and extending substantially in a first direction that is perpendicular to the upper surface of the substrate; a first source/drain region over the upper surface of the substrate; a second source/drain region over the upper surface of the substrate; and a channel region vertically extending in the first direction between the first source/drain region and the second source/drain region, wherein the channel region comprises an oxide semiconductor material. Along the first direction, the gate region covers a sidewall of the channel region.