Vertical Electronic Package Structure for Compact Thermal Routing
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Solution Overview
Problem
Conventional semiconductor packages face challenges in reducing volume and improving heat dissipation efficiency by making the second conductive element and/or the third conductive element between the parts of the electronic package in the structure of the semiconductor package, which are not addressed in existing technologies.
Innovation Solution
The electronic package design includes a first circuit structure, an electronic component set, and an encapsulating layer, with conductive elements connecting exposed active surfaces of stacked components to reduce height and enhance heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the encapsulating layer leaves a space on its top to accommodate the gold wire, then the electrical connection between chips and circuit structure is achieved, but the volume of the semiconductor package cannot be reduced
Solution Approach 1:
The patent transitions from planar wire routing to three-dimensional vertical stacking. Multiple chips are stacked in the vertical dimension with conductive elements extending through the encapsulating layer, eliminating the need for additional horizontal space and reducing overall package volume while maintaining electrical connectivity.
Solution Approach 2:
The patent implements a nested structure where multiple chips are stacked vertically within the encapsulating layer. The conductive elements pass through the encapsulating layer to connect chips at different levels, creating a compact nested arrangement that reduces package volume compared to traditional wire-bonding methods.
2Loss of energy
If the volume of the semiconductor package is increased to accommodate wire space, then electrical connections are established, but the heat dissipation efficiency deteriorates due to longer heat conduction path
Solution Approach 1:
The patent utilizes vertical stacking in the third dimension to reduce the horizontal heat conduction path. By stacking chips vertically and providing direct thermal pathways through the encapsulating layer, heat can escape more efficiently through the vertical dimension, improving heat dissipation without increasing package volume.
Solution Approach 2:
The patent merges the electrical connection function and thermal management function into a unified vertical stacking structure. The same conductive elements that provide electrical connectivity also serve as thermal pathways, eliminating the need for separate wire-bonding infrastructure and improving overall heat dissipation efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design significantly reduces the height of the electronic package and improves heat dissipation efficiency by shortening the path for heat conduction to the surface.
Implementation Method 1
the first electronic component is electrically connected to the first surface via a plurality of first conductive elements
Implementation Method 2
an encapsulating layer encapsulating the electronic component set and defined with a first encapsulating surface and a second encapsulating surface
Data Source
AI summary
An electronic package is provided and includes a first circuit structure having opposite first and second surfaces; an electronic component set including a first electronic component and a second electronic component and having opposite first and second sides, wherein the first electronic component is located on the first side and has opposite first active surface and first inactive surface, the second electronic component has opposite second active surface and second inactive surface, and a part of the second active surface protrudes and is exposed from an outside of the first electronic component to electrically connect to the first surface; and an encapsulating layer defining opposite first encapsulating surface and second encapsulating surface, wherein the second encapsulating surface is connected to the first surface. As such, the overall height of the electronic package can be reduced and the heat dissipation efficiency of the electronic package can be improved also.