Vertical Transistor Page Buffer for Nonvolatile Memory Area Reduction
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Solution Overview
Problem
The increasing storage capacity of nonvolatile memory devices leads to an excessive increase in the size of the page buffer, which compromises the operating performance and requires a larger peripheral circuit region, posing a challenge in maintaining efficient data processing and storage density.
Innovation Solution
Implementing a page buffer using vertical transistors within the peripheral circuit region, which allows for a more compact design by maximizing space utilization and reducing the size of the peripheral circuit region while maintaining efficient data processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of channel structures is increased to improve storage capacity, then storage capacity is improved, but the size of the peripheral circuit region increases excessively
Solution Approach 1:
The page buffer is moved from the peripheral circuit region to the lower surface of the first semiconductor substrate, utilizing the third dimension (vertical stacking) to relocate components. This dimensional transition allows the page buffer to be positioned below the memory cell region, effectively removing it from the peripheral circuit region and reducing its area occupation in the planar view.
Solution Approach 2:
The page buffer is nested within the semiconductor substrate structure by placing it on the lower surface, which is part of the overall device architecture. This nesting approach integrates the page buffer into the substrate's three-dimensional structure, allowing it to coexist with the memory cell region without occupying additional peripheral circuit space.
2Productivity
If the size of the page buffer is increased to handle greater data amounts, then data processing capability is improved, but the peripheral circuit region size increases excessively
Solution Approach 1:
The page buffer is relocated to the lower surface of the first semiconductor substrate, utilizing the vertical dimension to separate it from the peripheral circuit region. This allows the page buffer to maintain its data processing capability while occupying space that would otherwise be unavailable, effectively decoupling its size requirements from the peripheral circuit region constraints.
3Reliability
If the number of page buffers is increased to sense values from more memory cells, then sensing capability is improved, but the size of the peripheral circuit region increases excessively
Solution Approach 1:
The page buffers are positioned on the lower surface of the first semiconductor substrate through vertical stacking, which allows multiple page buffers to be implemented without proportionally increasing the peripheral circuit region area. This dimensional reorganization enables enhanced sensing capability while maintaining efficient space utilization in the peripheral circuit region.
Data Source
AI summary
A nonvolatile memory device includes a memory cell region and a peripheral circuit region disposed below the memory cell region. The peripheral circuits include a page buffer, a row decoder, and other peripheral circuits, wherein the page buffer is included in a page buffer block disposed on a lower surface of the first semiconductor substrate to be distinguished from other circuits included in the peripheral circuit region in a first direction perpendicular to an upper surface of the first semiconductor substrate, is connected to the memory cell region through a connection portion penetrating through the first semiconductor substrate, and includes a plurality of vertical transistors each defined by a source region, a channel region, and a drain region stacked in sequence in the first direction.