Vertical Parallel Plate Capacitor with Viabar Interconnects
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Solution Overview
Problem
Integrated circuits face challenges in achieving high capacitance density and reliability due to stringent minimum pitch requirements in back-end-of-line vertical parallel plate capacitors, leading to process difficulties and time-dependent dielectric breakdown issues.
Innovation Solution
The integration of a substrate with front-end-of-line circuitry and the formation of conductive levels with viabars that connect without contacting the conductive traces, allowing for sub-design rule spacing and increased capacitance density through vertically alternating conductive layers of opposite polarity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the finger pitch of the VPPCAP structure is reduced to achieve higher capacitance density, then capacitance density is improved, but process difficulties and reliability problems increase
Solution Approach 1:
The patent transitions from a conventional planar capacitor structure to a vertical parallel plate capacitor structure by stacking conductive plates in the vertical dimension. This dimensional change allows capacitance to be increased without reducing the horizontal finger pitch, thereby maintaining reliability while achieving higher capacitance density through vertical stacking of multiple conductive plates separated by dielectric layers.
Solution Approach 2:
The capacitor is segmented into multiple discrete conductive plates stacked vertically, rather than using a single large plate or reducing the pitch of horizontal fingers. Each conductive plate forms a separate capacitive element, and multiple such elements are stacked to achieve the desired total capacitance while maintaining adequate spacing between each plate to avoid reliability issues.
2Quantity of substance
If the finger pitch is reduced to meet minimum pitch requirements, then capacitance density is improved, but via protrusions causing time dependent dielectric breakdown occur
Solution Approach 1:
The invention moves the capacitance enhancement strategy from the horizontal plane (reducing finger pitch) to the vertical dimension (stacking plates). This eliminates the need for reduced pitch and associated via protrusion problems, as the vertical stacking provides adequate spacing between conductive elements while achieving high capacitance density.
Solution Approach 2:
Dielectric layers are introduced as intermediary materials between the stacked conductive plates. These dielectric layers provide electrical isolation and mechanical support, preventing direct contact between adjacent conductive plates and eliminating via protrusion issues while maintaining the vertical stacking architecture for high capacitance density.
3Ease of manufacture
If conventional planar capacitor structures are used, then process steps are simplified, but capacitance density is insufficient
Solution Approach 1:
The patent employs vertical stacking of conductive plates in the third dimension, transforming the conventional two-dimensional planar capacitor into a three-dimensional structure. This vertical architecture achieves high capacitance density without requiring additional lithography masks or complex planar processing steps, as it utilizes the existing multi-level metallization capability of advanced CMOS processes.
Solution Approach 2:
The vertical parallel plate capacitor structure utilizes the existing multi-level metallization infrastructure of advanced CMOS processes, making it compatible with standard fabrication flows. The structure serves multiple functions: achieving high capacitance density, utilizing available process capability, and maintaining compatibility with existing device architectures without requiring dedicated capacitor fabrication lines.
Data Source
AI summary
An integrated circuit system that includes: providing a substrate including front-end-of-line circuitry; forming a first conductive level including a first conductive trace over the substrate; forming a second conductive level spaced apart from the first conductive level and including a second conductive trace; and connecting the first conductive level to a third conductive level with a viabar that passes through the second conductive level without contacting the second conductive trace.