Vertical Pass Transistor Array for Non-Volatile Memory Integration
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Solution Overview
Problem
As memory devices become more multifunctional and require larger capacities and higher integration, the increased number of word lines stacked vertically leads to a larger area occupied by pass transistors, making it difficult to integrate peripheral circuits effectively, especially in a cell-over-periphery (COP) structure where the memory cell array is above the peripheral circuit.
Innovation Solution
The non-volatile memory device employs a pass transistor array with vertical pass transistors sharing a common drain and main contact, allowing for a reduced area occupation while maintaining high integration by stacking word lines and using a semiconductor layer structure with a COP configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of word lines is increased to achieve larger memory capacity, then the memory capacity is improved, but the area occupied by pass transistors increases making peripheral circuit integration difficult
Solution Approach 1:
The patent transitions from a planar arrangement of pass transistors to a three-dimensional vertical stacking configuration. Multiple pass transistors are stacked vertically along the first direction, allowing them to share common source and drain regions. This vertical dimensionality change enables the memory device to accommodate more word lines and pass transistors without proportionally increasing the planar area, thus resolving the contradiction between memory capacity and pass transistor area.
2Area of stationary object
If vertical pass transistors are used to reduce area, then the area occupation is reduced, but the complexity of sharing common drain and main contact increases
Solution Approach 1:
The patent merges multiple pass transistors into a vertical stack where they share common source and drain regions. Specifically, multiple pass transistors corresponding to different word lines share a common drain region and a common main contact structure. This merging approach reduces the total area by eliminating redundant source and drain regions, while the shared structure simplifies the overall device complexity compared to having separate contacts for each transistor.
Solution Approach 2:
The common drain region and main contact structure serve multiple functions simultaneously - they act as the drain for multiple pass transistors and provide electrical connection to multiple word lines. This multi-functionality allows the same structural elements to serve several purposes, reducing both area and complexity.
Data Source
AI summary
A non-volatile memory device including a memory cell array including a plurality of word lines stacked on a substrate in a first direction perpendicular to an upper surface of the substrate, and a common source line below the plurality of word lines, a plurality, of driving signal lines connected to a row decoder, and a plurality of pass transistor arrays each including a plurality of vertical pass transistors respectively connected the plurality of driving signal lines and the plurality of word lines, wherein each of the plurality of pass transistor arrays further include an active region including a drain to which at least two of the plurality of vertical pass transistors are simultaneously bonded, and a main contact applying a signal to the active region.