Vertical Conductive Pattern Layout for Narrow-Slit Memory Integration
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high integration and operational reliability due to limitations in the arrangement and isolation of memory cell transistors and conductive patterns, which affect the efficiency and performance of signal transmission.
Innovation Solution
The semiconductor device incorporates first and second vertical conductive patterns isolated by a slit, with half conductive patterns extending from each vertical pattern to enhance integration and reliability by minimizing the width of the slit and ensuring electrical connectivity through symmetrical conductive patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the slit width is minimized to increase integration density, then the degree of integration is improved, but the electrical characteristics of select transistors deteriorate
Solution Approach 1:
The conductive patterns are configured to extend in the first direction (vertical dimension) from the vertical conductive patterns, creating a three-dimensional arrangement that allows the slit to be narrow in the second direction while maintaining sufficient electrical connection area through vertical extension. This dimensional transition enables high integration without sacrificing transistor electrical characteristics.
Solution Approach 2:
The half conductive patterns are nested between the vertical conductive patterns and the bit lines, creating a compact structure where multiple conductive elements are arranged in close proximity. This nesting arrangement maximizes space utilization, allowing the slit width to be minimized while maintaining proper electrical connections for select transistor operation.
2Manufacturing precision
If the overlap between conductive patterns is reduced to improve manufacturing precision, then the manufacturing precision is improved, but the electrical connectivity deteriorates
Solution Approach 1:
The conductive patterns extend vertically in the first direction, creating a three-dimensional connection path. This vertical extension compensates for reduced horizontal overlap, ensuring that even with minimal overlap in the second direction (improving manufacturing precision), sufficient electrical connectivity is maintained through the extended vertical pathways.
Solution Approach 2:
The conductive patterns are configured with asymmetric dimensions: narrow width in the second direction (improving manufacturing precision) but extended length in the first direction (maintaining electrical connectivity). This asymmetric design allows the pattern to achieve both manufacturing precision and reliable electrical connection simultaneously.
Data Source
AI summary
A semiconductor device and a method of manufacturing a semiconductor device may be provided. The semiconductor device may include first and second vertical conductive patterns isolated from each other by a first slit. The semiconductor device may include at least one first half conductive pattern extending toward a first region disposed at one side of the first slit from the first vertical conductive pattern. The semiconductor device may include at least one second half conductive pattern extending toward a second region disposed at the other side of the first slit from the second vertical conductive pattern.