Vertical Semiconductor Patterns With Curved Silicide Contacts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional two-dimensional semiconductor elements face limitations in integration density due to the need for expensive equipment for miniaturization, limiting their performance and cost-effectiveness, prompting the exploration of three-dimensional semiconductor structures.
Innovation Solution
A semiconductor device with semiconductor patterns stacked perpendicular to a substrate, featuring mold insulating layers, silicide patterns, and metal conductive films, where the silicide patterns have curved sidewalls and side extension holes, allowing for increased integration density and improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If two-dimensional or planar semiconductor elements are used, then manufacturing processes are simpler, but the degree of integration is limited
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor elements to three-dimensional vertically stacked structures. Multiple semiconductor patterns are stacked in the vertical direction (third direction) perpendicular to the substrate, enabling increased integration density without requiring further miniaturization of individual elements. This dimensional change allows more elements to be packed into the same footprint area.
2Quantity of substance
If pattern miniaturization is pursued to increase integration density, then more elements can be packed, but ultra-expensive apparatuses are required
Solution Approach 1:
Instead of continuing to miniaturize patterns in the planar direction which requires expensive equipment, the patent stacks semiconductor patterns vertically in the third direction. This approach increases integration density by utilizing the vertical dimension, thereby avoiding the need for ultra-expensive miniaturization apparatuses while achieving higher element counts.
Solution Approach 2:
The patent employs different material properties and structural characteristics at different locations. Silicide patterns with curved sidewalls are formed at specific positions, and side extension holes are created in certain regions to enable capacitance formation. This localized differentiation allows optimized performance without requiring expensive global miniaturization processes.
3Quantity of substance
If three-dimensional semiconductor structures are implemented, then integration density increases, but device complexity increases
Solution Approach 1:
The three-dimensional structure is segmented into repeating units consisting of semiconductor patterns, mold insulating layers, and associated components stacked in the vertical direction. Each unit cell can be independently formed and then replicated, which simplifies the manufacturing process despite the overall three-dimensional complexity. The segmentation into discrete stackable units makes the complex structure more manageable.
Solution Approach 2:
Mold insulating layers are formed in advance between the semiconductor patterns during the stacking process. These pre-formed insulating layers simplify subsequent processing steps by providing built-in isolation and structural definition, thereby reducing the overall manufacturing complexity despite the three-dimensional architecture.
4Ease of manufacture
If conventional planar structures are used, then manufacturing processes are simpler, but performance and reliability are limited
Solution Approach 1:
The patent achieves improved performance and reliability by transitioning to three-dimensional vertically stacked semiconductor patterns. This dimensional change increases the effective channel length and improves device characteristics without requiring complex manufacturing processes, as the vertical stacking can be achieved through standard deposition and etching techniques.
Data Source
AI summary
Provided a semiconductor device comprises, a plurality of semiconductor patterns spaced in a first direction; a plurality of mold insulating layers between the plurality of semiconductor patterns, a plurality of silicide patterns contacting the plurality of semiconductor patterns; and a plurality of first metal conductive films between the plurality of mold insulating layers and connected to each of the silicide patterns, wherein each of the silicide patterns includes a first sidewall that faces the semiconductor pattern, and a second sidewall which faces the first metal conductive film, the first sidewall of the silicide pattern and the second sidewall of the silicide pattern extends in the first direction, and the first sidewall of the silicide pattern and the second sidewall of the silicide pattern are curved surfaces.