Vertical PCRAM Cell Layout for Higher Density Double-Side Heating
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current phase change random access memory (PCRAM) technologies face challenges in increasing areal storage cell density due to physical limitations and device speed constraints, particularly because the integration of a second heating FET to enhance current density increases cell area and requires high-temperature fabrication processes that can damage the storage layer bond.
Innovation Solution
The implementation of an embedded double side heating PCRAM device with a vertical architecture, utilizing silicon on insulator (SOI) substrates and a flipped wafer process to separate FET logic and phase change material fabrication, allowing for optimal processing temperatures and tighter packing of storage cells with a second heating transistor in the storage layer for improved areal density and heating efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a second heating FET is integrated to enhance current density, then switching speed is improved, but cell area increases
Solution Approach 1:
The patent transitions from a planar architecture to a vertical architecture, stacking the FET logic layer and storage layer in different vertical dimensions. This allows the second heating FET to be integrated in the storage layer without increasing the lateral cell footprint, thereby improving switching speed while maintaining compact cell area.
Solution Approach 2:
The patent segments the PCRAM device into distinct layers: a FET logic layer containing the first heating FET and a storage layer containing the phase change material and second heating FET. This segmentation allows independent optimization of each layer and enables the second heating FET to be added without proportionally increasing the overall cell area.
2Reliability
If high-temperature fabrication processes are used for FET logic, then transistor performance is improved, but storage layer bond degrades
Solution Approach 1:
The patent separates the fabrication process into two stages: first fabricating the FET logic layer on a first wafer at high temperatures, then bonding it to a carrier wafer and fabricating the storage layer at lower temperatures. This segmentation allows each layer to be processed at its optimal temperature without damaging the bond between layers.
Solution Approach 2:
The FET logic layer is fabricated and bonded to the carrier wafer before the storage layer is formed. This preliminary action ensures that the FET logic is already optimized with high-temperature processing, and the subsequent low-temperature storage layer fabrication will not degrade the bond or the FET performance.
3Quantity of substance
If vertical architecture with flipped wafer process is used to separate fabrication temperatures, then areal density is improved, but device complexity increases
Solution Approach 1:
The patent divides the device into separable layers fabricated on different wafers, allowing independent optimization of each layer's fabrication process. The FET logic layer and storage layer are made on separate first and second wafers, then bonded together, enabling complex functionality without requiring a single complex fabrication sequence.
Solution Approach 2:
The carrier wafer acts as an intermediary substrate that receives the FET logic layer and provides a platform for subsequent storage layer fabrication. This intermediary allows the decoupling of high-temperature FET fabrication from low-temperature storage layer fabrication, enabling areal density improvement through vertical stacking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher areal storage cell density and improved heating efficiency by segregating high-temperature FET logic and low-temperature phase change material fabrication, preventing bond degradation and allowing for closer packing of storage cells while maintaining enhanced switching current.
Implementation Method 1
Phase change random access memory (PCRAM) device
Implementation Method 2
at least one heating FET for each storage cell of the PCRAM that is electrically connected to heat the phase change material of the storage cell
Data Source
AI summary
In fabrication of a phase change random access memory (PCRAM), a field effect transistor (FET) logic layer is formed on a first wafer, including a heating FET for each storage cell. The FET logic layer is transferred from the first wafer to a carrier wafer. Thereafter, a storage layer of the PCRAM is formed on the exposed surface of the FET logic layer, including a region of a phase change material for each storage cell that is electrically connected to a channel of the heating FET of the storage cell. The storage layer further includes a second heating transistor for each storage cell that is electrically connected to a channel of the second heating transistor.