Vertical Pillar Semiconductor Device Reducing Bit Line Capacitance
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Solution Overview
Problem
Conventional semiconductor devices with horizontal transistors face challenges in reducing the overall area of semiconductor memory apparatuses, making it difficult to increase productivity by reducing the number of devices per wafer.
Innovation Solution
The semiconductor device employs vertical pillars with a vertical channel region, where a first bit line made of metal silicide is formed inside the pillars, and a second bit line with a titanium nitride and tungsten structure is formed on the sidewalls, along with an interlayer insulating film and spacers, to reduce capacitance and increase process margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional horizontal transistors are used, then the transistor structure is simple to manufacture, but the overall area of the semiconductor memory apparatus cannot be reduced
Solution Approach 1:
The patent transitions from conventional horizontal transistors to vertical transistors by changing the channel direction from horizontal to vertical. The channel region extends in the vertical direction between source and drain regions, allowing the transistor to occupy less planar area while maintaining functionality. This dimensional change enables higher density memory structures.
Solution Approach 2:
The bit line is formed inside the pillar structure, nested within the vertical channel region. This nested configuration allows the bit line to be positioned within the pillar rather than requiring separate external routing, reducing the overall area occupied by each memory cell.
2Object-generated harmful factors
If bit lines are formed outside pillars, then the manufacturing process is simpler, but the capacitance between adjacent bit lines increases
Solution Approach 1:
The bit line is formed inside the pillar structure, nested within the vertical channel region. This nested configuration allows the bit line to be positioned within the pillar rather than requiring separate external routing, reducing the overall area occupied by each memory cell and the capacitance between adjacent bit lines.
Solution Approach 2:
An interlayer insulating film is introduced as an intermediary layer between adjacent pillars containing bit lines. This insulating film effectively reduces the capacitance between adjacent bit lines by providing electrical isolation, while still allowing for a compact structure.
3Area of stationary object
If vertical transistors are used, then the area per semiconductor cell is reduced, but the manufacturing precision requirements increase
Solution Approach 1:
A pillar hard mask is formed on the semiconductor substrate before pillar formation. This preliminary masking step defines the pillar patterns and positions, ensuring precise pillar formation. The hard mask serves as a template that guides the subsequent etching process to create accurately positioned vertical pillars.
Solution Approach 2:
The interlayer insulating film is formed between pillars during the manufacturing process, serving as a preliminary isolation structure. This pre-formed insulating layer ensures proper electrical isolation between adjacent pillars and bit lines, maintaining manufacturing precision for capacitance reduction.
Data Source
AI summary
A semiconductor device and a method for fabricating the same are provided to enable a bit line to be formed easily, increase a bit line process margin and reduce capacitance between the adjacent bit lines. The semiconductor device comprises: a first pillar and a second pillar each extended vertically from a semiconductor substrate and including a vertical channel region; a first bit line located in the lower portion of the vertical channel region inside the first pillar and the second pillar; and an interlayer insulating film located between the first pillar and the second pillar that include the first bit line.