4F2 Vertical Pillar Bit Line Resistance Reduction
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Solution Overview
Problem
The development of highly integrated semiconductor memory devices faces challenges in reducing the unit area of a cell storing one bit of data, particularly in forming a 4F2-sized unit cell with a vertical channel structure, which is structurally complex and difficult to fabricate.
Innovation Solution
A semiconductor device and method involving a first junction region at the bottom of a vertical pillar, a bit line below the junction region, an insulation film, a polysilicon layer, and a barrier conductive layer, along with a gate oxide film and second junction region, are used to form a 4F2-sized structure, including ion implantation and heat treatment processes to create a vertical channel transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a vertical channel structure is used to achieve 4F2-sized unit cell, then the cell area is reduced, but the fabrication complexity increases significantly
Solution Approach 1:
The device is segmented into distinct functional regions: a first junction region at the bottom of the vertical pillar, a second junction region at the top, and a channel region in between. This segmentation allows each region to be formed through targeted ion implantation processes, simplifying the overall fabrication while achieving the compact 4F2-sized unit cell structure.
Solution Approach 2:
The invention transitions from traditional planar horizontal source-drain configuration to a vertical three-dimensional structure. The channel extends vertically through the pillar, with source and drain regions positioned at different heights, enabling compact area utilization while maintaining manufacturability through standard vertical processing techniques.
2Manufacturing precision
If ion implantation is used to form junction regions, then the junction depth and doping precision are improved, but the process time increases
Solution Approach 1:
The first junction region is formed through ion implantation before the vertical pillar structure is fully defined. This preliminary doping action establishes the bottom source/drain region early in the process, allowing subsequent steps to build upon this foundation without requiring re-doping, thereby reducing total process time while maintaining precise junction depth control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of a 4F2-sized semiconductor device with reduced bit line resistance and capacitance, improving data retention and sensing margin, while simplifying the fabrication process of vertical channel transistors.
Implementation Method 1
forming a first junction region at the bottom of the silicon layer by implanting ions in the silicon layer
Implementation Method 2
forming a crystalline silicon layer by performing solid phase epitaxy on the undoped amorphous silicon layer
Data Source
AI summary
A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a first junction region formed at the bottom of a vertical pillar, a bit line formed below the first junction region, and an insulation film formed below the bit line. As a result, the 4F2-sized semiconductor device is provided and the bit line is configured in the form of a laminated structure of a conductive layer and a polysilicon layer, so that bit line resistance is reduced. In addition, the semiconductor device reduces ohmic contact resistance by forming silicide between the conductive layer and the polysilicon layer, and includes an insulation film at a position between the semiconductor substrate and the bit line, resulting in reduction of bit line capacitance. Therefore, the sensing margin of the semiconductor device is increased and the data retention time is also increased.