Vertical Pillar Semiconductor Device Gate Control
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Solution Overview
Problem
As semiconductor devices integrate more densely, the short channel effect increases leakage current and reduces breakdown voltage, making it difficult to control MOS transistors effectively due to the reduced width of semiconductor pillars in vertical type semiconductor devices.
Innovation Solution
A vertical pillar semiconductor device with a multi-channel structure is developed, featuring a substrate divided into active and isolation regions, channel patterns protruding from the active region, a gate insulation layer, and a gate electrode that encloses the channel patterns, along with an etch stop layer and insulating interlayers, allowing for increased on-current without expanding the horizontal substrate area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the width of the semiconductor pillar is reduced to achieve higher integration and reduce leakage current, then the leakage current is reduced and integration degree is improved, but the channel region area is decreased and on-current is reduced
Solution Approach 1:
The patent transitions from a planar channel structure to a vertical channel structure by forming channel regions along the thickness direction of the semiconductor layer. This dimensional change allows the channel to extend vertically through multiple layers, increasing the effective channel area without expanding the horizontal footprint, thereby maintaining on-current while reducing leakage current through better gate control.
Solution Approach 2:
The patent divides the semiconductor structure into multiple layers with multiple channel regions formed in different layers. Each layer contains channel regions that are electrically connected, creating a segmented vertical channel structure. This segmentation allows the total channel area to be distributed across multiple layers, maintaining high on-current while keeping each individual layer's horizontal area small for high integration.
2Area of moving object
If the channel length is reduced to increase integration density, then the device size is reduced, but the short channel effect increases causing higher leakage current and lower breakdown voltage
Solution Approach 1:
The patent extends the channel in the vertical dimension rather than the horizontal dimension. By forming channel regions that extend through the thickness of the semiconductor layer and connecting multiple layers vertically, the effective channel length increases without increasing the horizontal device footprint. This vertical extension provides better gate control over the channel, suppressing the short channel effect while maintaining compact device size.
Solution Approach 2:
The patent nests multiple channel regions within a vertical stack structure, where channel regions in different layers are positioned one above another and electrically connected. This nested arrangement allows the channels to be contained within a compact vertical space, increasing the effective channel area for high on-current while keeping the horizontal device area small for high integration density.
3Quantity of substance
If multiple channel patterns are formed in parallel to increase on-current, then the on-current is increased, but the horizontal area of the substrate is increased
Solution Approach 1:
The patent forms multiple channel regions in the vertical dimension by creating channels in different layers and connecting them vertically. This vertical stacking approach allows multiple channels to be packed into a small horizontal area, increasing the total channel area for high on-current while minimizing the substrate area required.
Solution Approach 2:
The patent nests multiple channel regions within a compact vertical structure, where channels from different layers are positioned one above another and electrically connected through contact holes. This nested configuration enables high on-current through multiple parallel channels while confining the structure to a small horizontal footprint, achieving high integration density.
Data Source
AI summary
A vertical pillar semiconductor device may include a substrate, a group of channel patterns, a gate insulation layer pattern and a gate electrode. The substrate may be divided into an active region and an isolation layer. A first impurity region may be formed in the substrate corresponding to the active region. The group of channel patterns may protrude from a surface of the active region and may be arranged parallel to each other. A second impurity region may be formed on an upper portion of the group of channel patterns. The gate insulation layer pattern may be formed on the substrate and a sidewall of the group of channel patterns. The gate insulation layer pattern may be spaced apart from an upper face of the group of channel patterns. The gate electrode may contact the gate insulation layer and may enclose a sidewall of the group of channel patterns.