Vertical Pillar Memory Cell Array Design for High Density
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Solution Overview
Problem
Current resistive memory devices face limitations in integration density due to horizontal transistor structures and high operation voltages required by diodes, which also lead to word line resistance variations and 'word line bouncing' issues.
Innovation Solution
A variable resistive memory device with a memory cell array design featuring vertically arranged active pillars surrounded by word lines and inter-pattern insulating layers, allowing for reduced spacing between pillars and lower operation voltages, thereby enhancing integration density and current drivability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If horizontal transistor structures are used in memory devices, then device fabrication is simpler, but integration density cannot be increased sufficiently
Solution Approach 1:
The patent transitions from horizontal transistor structures to vertical transistor structures, changing the spatial dimension of device arrangement. This vertical configuration allows multiple memory cells to be stacked in the vertical direction, significantly increasing integration density while maintaining fabrication feasibility through adapted manufacturing processes
2Device complexity
If diodes are used as access devices in resistive memory, then device structure is simpler, but operation voltage must be 1.1 V or more
Solution Approach 1:
The patent changes the fundamental parameter of the access device from diode to transistor, which fundamentally alters the voltage characteristics. The transistor's gate control mechanism enables operation at lower voltages (below 1.1 V) by providing precise control over current flow, thereby reducing energy consumption while accepting increased device complexity
3Ease of manufacture
If diodes are formed on word lines in memory devices, then access device fabrication is simpler, but word line resistance changes according to cell positions
Solution Approach 1:
The patent applies local quality by positioning transistors at specific locations (at the ends of word lines rather than distributed along them) and using inter-pattern insulating layers strategically. This localized arrangement ensures uniform word line resistance across all cell positions by preventing resistance variations that occur when diodes are formed at different locations along the word line
4Power
If active pillars are arranged surrounded by word lines in traditional layout, then current drivability is sufficient, but layout area cannot be reduced
Solution Approach 1:
The patent merges multiple functional elements by having word lines serve dual purposes: they act as both the access line for selecting memory cells and as the gate electrode for the vertical transistors. This merging eliminates redundant structures and reduces the overall layout area while maintaining sufficient current drivability through the vertical transistor configuration
Data Source
AI summary
A memory cell array and a resistive variable memory device including the memory cell array are provided. The memory cell array includes a memory group. The memory cell array includes a pair of word lines, an inter-pattern insulating layer interposed between the pair of word lines, and a plurality of active pillars, each having one side contacted with the inter-pattern insulating layer and other sides surrounded by the word line.