Vertical Pillar Nonvolatile Memory Reducing Unit Cell Area
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Solution Overview
Problem
Conventional nonvolatile semiconductor memory devices face challenges in achieving high integration due to larger feature sizes and inefficient data storage capabilities compared to volatile memory devices like SRAM and DRAM.
Innovation Solution
The development of a nonvolatile semiconductor memory device with vertical channel transistors, featuring pillars on a semiconductor substrate with word lines and memory layers that include tunneling, charge storage, and blocking insulation films, allowing for the storage of two bits of information in a unit cell that occupies half the area of conventional memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional flash memory structures are used, then data storage capability is achieved, but feature size is larger and integration level is lower
Solution Approach 1:
The patent transitions from planar memory cells to vertical channel transistors with pillars protruding from the substrate. Word lines are positioned on the sidewalls of pillars rather than above them, creating a three-dimensional structure that reduces the footprint of each memory cell and enables higher integration density
Solution Approach 2:
The memory device is divided into multiple pillars arranged in an array, with each pillar serving as an independent vertical channel transistor. This segmentation allows parallel processing and increases the overall storage capacity within a smaller area
2Quantity of substance
If conventional flash memory structures are used, then data storage is achieved, but unit cell area is larger
Solution Approach 1:
By standing vertical channel transistors on pillars and positioning word lines on sidewalls, the patent reduces the planar footprint of each memory cell while maintaining the necessary functional components for data storage
Solution Approach 2:
The patent nests multiple functional layers within the vertical structure of pillars, including tunnel insulation films, charge trapping films, and blocking insulation films interleaved within the pillar material itself, maximizing space utilization
3Productivity
If vertical channel transistors with sidewall word lines are used, then integration level is improved, but device complexity increases
Solution Approach 1:
The complex three-dimensional structure is fabricated through sequential segmentation of simpler steps: forming pillars, depositing memory layers, positioning word lines on sidewalls, and creating bit lines. Each step builds upon the previous one, making the complex structure manufacturable
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables a higher level of integration by reducing the feature size of each unit storage element, allowing for more efficient data storage and improved operational reliability by preventing the floating body effect.
Implementation Method 1
In storing or erasing data, electric charges are injected into or emitted from a specific cell by supplying appropriate voltages to the corresponding word line WL and bit line BL of the cell
Implementation Method 2
Floating-trap flash memory devices store data by injecting electric charges into trap sites formed within non-conductive charge-trapping layers between word lines and the semiconductor substrate
Data Source
AI summary
A nonvolatile semiconductor memory device includes a plurality of pillars protruding upward from a semiconductor substrate and having respective top surfaces and opposing sidewalls, a bit line on the top surfaces of the pillars and connecting a row of the pillars along a first direction, a pair of word lines on the opposing sidewalls of one of the plurality of pillars and crossing beneath the bit line, and a pair of memory layers interposed between respective ones of the pair of word lines and the one of the plurality of pillars. Methods of fabricating a nonvolatile semiconductor memory device include selectively etching a semiconductor substrate to form pluralities of stripes having opposing sidewalls and being arranged along a direction, forming memory layers and word lines along the sidewalls of the stripes selectively etching the stripes to form a plurality of pillars, and forming a bit line connecting the pillars and crossing above the word lines.