Vertical Semiconductor Pillar Structure for Dense Memory Integration
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Solution Overview
Problem
The challenge in semiconductor technology is to develop miniaturized, high-performance, and highly integrated transistors while maintaining or improving the characteristics of the unit elements while reducing their size and footprint.
Innovation Solution
A semiconductor device is fabricated with semiconductor pillars arranged in specific directions, featuring insulating layers, conductive lines, and storage nodes, utilizing a method that includes forming sacrificial layers, etching processes, and depositing conductive materials to create a vertical channel structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional planar transistor structures are used, then manufacturing process is simpler, but device area is larger and integration density is lower
Solution Approach 1:
The patent transitions from conventional planar (2D) transistor structures to vertical (3D) structures by forming semiconductor pillars extending in the thickness direction. This dimensional change allows multiple transistors to be stacked vertically, significantly reducing the footprint area while maintaining functional complexity through multi-layer gate electrodes and conductive lines arranged in three-dimensional space
2Productivity
If transistor size is reduced, then integration density increases, but manufacturing precision requirements become more stringent
Solution Approach 1:
The patent forms sacrificial layers (first and second sacrificial layers) before forming the semiconductor pillars. These sacrificial layers serve as preliminary structures that define the pillar positions and dimensions, enabling precise formation of small-scale pillars through selective etching while maintaining manufacturing feasibility through the sacrificial layer template approach
Solution Approach 2:
The patent introduces sacrificial layers as intermediary structures that facilitate the formation of precise semiconductor pillars. The sacrificial layers act as temporary mediators during the fabrication process, enabling accurate pattern transfer and dimensional control that would be difficult to achieve directly at such small scales, after which they are selectively removed
3Reliability
If vertical channel structure is implemented, then current transfer capability improves, but device complexity increases
Solution Approach 1:
The patent segments the gate structure into multiple gate electrodes (first gate electrode, second gate electrode, third gate electrode) that can be independently controlled. This segmentation allows different gate electrodes to control different portions of the vertical channel, improving current transfer capability through enhanced electrostatic control while managing complexity through modular gate design
Solution Approach 2:
The patent designs conductive lines and gate electrodes to serve multiple functions: the first and second gate electrodes control the vertical channel current, the third gate electrode provides additional control, and conductive lines serve as both interconnects and control elements. This multi-functionality reduces the need for separate dedicated structures, managing device complexity while achieving superior current transfer capability
Data Source
AI summary
A semiconductor device may include a substrate; a plurality of semiconductor pillars disposed over the substrate and arranged in a first direction and a second direction crossing the first direction; an insulating layer pattern disposed between the substrate and the semiconductor pillars and extending in the second direction; a first conductive line disposed between the insulating layer pattern and the semiconductor pillars and extending in the second direction; a second conductive line formed over sidewalls of the semiconductor pillars and extending in the first direction; and a storage node disposed over each of the semiconductor pillars.