Vertical Epitaxial Silicon Pillar Charge Storage Transistors
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Solution Overview
Problem
Existing memory devices are expensive to fabricate and lack scalability due to limitations in charge storage transistor design, particularly in forming arrays of charge storage devices such as polysilicon floating gate or charge trap devices.
Innovation Solution
The formation of a pillar of epitaxial silicon on a layer of silicon, with multiple gates constructed around it to create charge storage transistors, allowing for the fabrication of scalable and cost-effective arrays of vertical NAND strings in a three-dimensional NAND flash integrated circuit chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional charge storage transistor designs are used, then fabrication processes are established, but fabrication costs are high and scalability is limited
Solution Approach 1:
The patent transitions from planar (2D) charge storage transistor design to vertical (3D) architecture by forming pillars extending through multiple semiconductor layers. This dimensional change enables higher density and scalability while maintaining fabrication compatibility, directly addressing the contradiction between ease of manufacture and productivity.
2Quantity of substance
If arrays of charge storage devices are formed, then memory capacity increases, but fabrication complexity and cost increase
Solution Approach 1:
The patent segments the memory structure into repeating vertical units (pillars with embedded charge storage nodes) that can be densely packed in arrays. Each pillar is formed through standardized processes, and the segmented architecture allows systematic scaling of memory capacity without proportionally increasing fabrication complexity.
Solution Approach 2:
The vertical pillar structure serves multiple functions simultaneously: it provides mechanical support, electrical isolation through tunnel oxide, charge storage through floating gates or charge trap layers, and structural template for array formation. This multi-functionality increases memory capacity while avoiding proportional increases in fabrication complexity.
3Reliability
If vertical NAND strings are formed with improved coupling, then transistor efficiency increases, but fabrication precision requirements increase
Solution Approach 1:
The patent performs preliminary actions during pillar formation by depositing tunnel oxide and floating gate materials conformally on the pillar surfaces before final gate electrode formation. This preliminary structuring establishes precise coupling geometries early in the process, ensuring reliable transistor efficiency while managing fabrication precision requirements through process integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces fabrication costs and enables further scaling of charge storage transistors by improving the coupling between epitaxial silicon pillars and control gates, resulting in high-quality single-crystal silicon and tunnel oxide layers, enhancing the efficiency and scalability of memory devices.
Implementation Method 1
formation of a pillar of epitaxial silicon on a layer of silicon
Implementation Method 2
high-quality single-crystal silicon and tunnel oxide layers
Data Source
AI summary
Methods of fabricating charge storage transistors are described, along with apparatus and systems that include them. In one such method, a pillar of epitaxial silicon is formed. At least first and second charge storage nodes (e.g., floating gates) are formed around the pillar of epitaxial silicon at different levels. A control gate is formed around each of the charge storage nodes. Additional embodiments are also described.