Vertical Pillar Semiconductor Device for High Density Integration
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Solution Overview
Problem
Conventional two-dimensional semiconductor devices face limitations in integration density due to the high cost of forming fine patterns, and three-dimensional semiconductor devices are expensive per bit, necessitating a cost-effective process for increasing integration density.
Innovation Solution
A semiconductor device with vertically stacked word lines and insulating patterns, including a substrate with a cell array region and a dummy region, featuring vertical pillars and residual sacrificial patterns, is fabricated using a method involving alternately stacked sacrificial and insulating layers, with specific thickness ratios to optimize integration density and reduce costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional two-dimensional semiconductor devices are used to achieve high integration density, then fine pattern formation is required, but extremely high-priced apparatuses are needed
Solution Approach 1:
The patent transitions from conventional two-dimensional planar structures to three-dimensional vertical structures by stacking word lines and insulating patterns vertically. This dimensional change enables higher integration density without requiring extremely fine lateral patterning, thereby reducing fabrication costs while maintaining manufacturing precision.
2Manufacturing precision
If three-dimensional semiconductor devices are developed to overcome integration density limitations, then integration density improves, but cost per bit becomes expensive
Solution Approach 1:
The patent forms insulating patterns between word lines before completing the vertical stacking process. This preliminary action simplifies subsequent fabrication steps and reduces the complexity of forming three-dimensional structures, thereby lowering the cost per bit while achieving high integration density.
Solution Approach 2:
The patent optimizes the thickness ratios of sacrificial and insulating layers to control the vertical dimensions and spacing of stacked structures. By carefully adjusting these parameters, the device achieves high integration density with simplified processing, reducing fabrication costs.
3Manufacturing precision
If vertical stacking of word lines is implemented to increase integration density, then three-dimensional structure is formed, but process complexity increases
Solution Approach 1:
The patent divides the vertical stacking process into discrete segments: forming sacrificial layers, depositing insulating layers, removing sacrificial layers to create voids, and filling voids with conductive materials. This segmentation transforms a complex three-dimensional fabrication process into a series of simple, repeatable two-dimensional steps, reducing overall process complexity.
Data Source
AI summary
A semiconductor device includes word lines vertically stacked on top of each other on a substrate, insulating patterns between the word lines, a vertical pillar connected to the substrate, and residual sacrificial patterns on the substrate at sides of the word lines. The vertical pillar penetrates the word lines and the insulating patterns. Each of the insulating patterns includes a first portion between the word lines and a second portion extending from the first portion and between the residual sacrificial patterns. A first thickness of the first portion is smaller than a second thickness of the second portion.