Vertical Pillar Transistor Gate Masking for Leakage Reduction
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Solution Overview
Problem
The challenge lies in manufacturing high-performance vertical-type semiconductor devices with pillar transistors, which face issues such as increased leakage current, non-uniform electrical properties due to crystal defects, and complex processes for forming gates and source/drain regions, making it difficult to achieve reliable memory devices with integrated structures.
Innovation Solution
A semiconductor device with a single-crystalline pillar-shaped semiconductor pattern on a substrate, surrounded by a gate with a linear shape and impurity regions, along with a mask pattern and spacers, is developed, allowing for improved control of channel length and reduced process failures, enabling efficient data storage and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If a vertical-type pillar transistor is formed in a semiconductor pattern, then channel length can be increased without widening horizontal area, but crystal defects in the semiconductor pattern cause non-uniform electrical properties and increased leakage current
Solution Approach 1:
The patent transitions from horizontal channel formation to vertical channel formation by creating pillar-shaped semiconductor patterns extending in the vertical direction. This dimensional change allows channel length extension without increasing horizontal footprint, while the gate electrode completely surrounds the pillar to provide uniform electrical control along the vertical channel
Solution Approach 2:
The patent employs a composite structure combining a semiconductor pattern (channel region) completely surrounded by a gate electrode, forming a vertical transistor architecture. This composite arrangement enables the gate to control the vertical channel from all sides, improving electrical property uniformity while maintaining the vertical channel length advantage
2Productivity
If vertical-type pillar transistors are formed in an array structure, then integration density is improved, but process complexity increases and process failures increase
Solution Approach 1:
The patent divides the semiconductor substrate into multiple isolated pillar-shaped patterns arranged in arrays, with each pillar forming an independent vertical transistor. This segmentation allows standardized manufacturing processes to be applied uniformly across all transistors, reducing overall process complexity while achieving high integration density
Solution Approach 2:
The patent changes the geometric parameters of the transistor structure by forming vertical pillars with controlled heights and diameters, allowing optimization of electrical characteristics while maintaining a simplified array fabrication process that can be manufactured using standard semiconductor processing techniques
3Productivity
If channel length is reduced to increase integration, then more devices fit on substrate, but short channel effects increase causing leakage current and threshold voltage decrease
Solution Approach 1:
The patent resolves the short channel effect problem by moving the channel from horizontal to vertical orientation. The vertical pillar structure allows the channel length to extend in the vertical direction while maintaining a compact horizontal footprint, enabling high integration without suffering from horizontal short channel effects
Solution Approach 2:
The patent creates a composite vertical transistor structure where the gate electrode completely surrounds the vertical channel pillar, providing three-dimensional gate control. This configuration effectively suppresses short channel effects by controlling the vertical channel from all sides, preventing leakage current and threshold voltage degradation while maintaining small device dimensions for high integration
Data Source
AI summary
In a vertical-type semiconductor device, a method of manufacturing the same and a method of operating the same, the vertical-type semiconductor device includes a single-crystalline semiconductor pattern having a pillar shape provided on a substrate, a gate surrounding sidewalls of the single-crystalline semiconductor pattern and having an upper surface lower than an upper surface of the single-crystalline semiconductor pattern, a mask pattern formed on the upper surface of the gate, the mask pattern having an upper surface coplanar with the upper surface of the single-crystalline semiconductor pattern, a first impurity region in the substrate under the single-crystalline semiconductor pattern, and a second impurity region under the upper surface of the single-crystalline semiconductor pattern. The vertical-type pillar transistor formed in the single-crystalline semiconductor pattern may provide excellent electrical properties. The mask pattern is not provided on the upper surface of the single-crystalline semiconductor pattern in the second impurity region, to thereby reduce failures of processes.