Vertical Pillar Transistors on Single Crystal Silicon
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Solution Overview
Problem
The high cost and potential defects associated with using Silicon on Insulator (SOI) wafers for manufacturing floating body memories, which are necessary for stable semiconductor operations, lead to increased manufacturing costs and reduced reliability due to the oxygen ion implantation process for forming buried oxide layers.
Innovation Solution
The semiconductor device employs a vertical pillar structure formed on ordinary single crystal silicon wafers, eliminating the need for SOI wafers and avoiding defects by forming gates on one surface of the silicon pillars and connecting drain areas perpendicular to each other, with insulation layers used to connect gates and prevent full depletion of the channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SOI wafers are used to manufacture floating body memories, then the floating body memory structure can be realized, but the manufacturing cost increases and defects occur due to oxygen ion implantation
Solution Approach 1:
The invention extracts and removes the buried oxide layer from the SOI structure, retaining only the silicon layer and substrate. This eliminates the harmful oxygen ion implantation process while preserving the essential floating body memory functionality, thereby reducing manufacturing cost and avoiding defects associated with SOI wafer fabrication
Solution Approach 2:
The invention replaces expensive SOI wafers with ordinary single crystal silicon wafers, which are cheaper and more readily available. By eliminating the need for complex SOI fabrication processes including oxygen ion implantation and annealing, the invention significantly reduces manufacturing cost while achieving the same floating body memory effect
2Reliability
If SOI wafers are used with buried oxide layer formation, then floating body memory structure is achieved, but defects are caused in silicon due to oxygen ion implantation process
Solution Approach 1:
The invention removes the buried oxide layer that causes harmful effects during fabrication. By eliminating this layer and its associated oxygen ion implantation process, the invention prevents silicon defects while maintaining the functional requirements for floating body memory operation
Solution Approach 2:
The invention converts the potential harm of having no oxide layer protection into a benefit by using the direct silicon-silicon interface to achieve better carrier confinement and reduced interface states, improving silicon crystal integrity and device reliability
3Ease of manufacture
If vertical pillar structure is used on ordinary silicon wafers, then manufacturing cost is reduced, but new fabrication challenges arise
Solution Approach 1:
The invention transitions from planar transistor structures to vertical pillar structures, utilizing the third dimension (vertical direction) to achieve higher integration density. This dimensional change allows standard silicon wafers to support complex 3D transistor architectures without requiring expensive SOI substrates
Solution Approach 2:
The invention segments the transistor structure into distinct vertical components (gate, source, drain) arranged along the vertical axis of the pillar. This segmentation enables independent optimization of each component and simplifies the fabrication process by allowing sequential formation of each segment using standard semiconductor processing techniques
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs and improves the reliability and operation characteristics of semiconductor devices by avoiding the use of costly SOI wafers and preventing defects, enabling the production of highly integrated semiconductor devices.
Implementation Method 1
annealing the resultant silicon substrate formed with the source areas, such that drain areas of vertical pillar transistors arranged in another direction perpendicular to one direction are connected with one another
Data Source
AI summary
A semiconductor device includes vertical pillar transistors formed in respective silicon pillars of a silicon substrate. The gates of the vertical pillar transistor are selectively formed on a single surface of lower portions of the silicon pillars, and drain areas of the vertical pillar transistors are connected with one another.