Vertical Semiconductor Pillars With GAA Gates for Precise Doping
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Solution Overview
Problem
Existing semiconductor manufacturing processes face challenges in achieving high integration density and accurate doping in vertical transistor structures due to their complex process difficulty.
Innovation Solution
A method for fabricating a semiconductor structure involving the formation of semiconductor pillars on a substrate, followed by the creation of gates on the middle sidewalls and precise doping implantation using the gates as masks to form source and drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertical transistor structures are used to improve integration density, then the integration level increases, but the process difficulty increases significantly
Solution Approach 1:
The patent applies preliminary action by forming gates on the sidewalls of semiconductor pillars before performing doping implantation. This sequence allows the gates to serve as precise masks that define the doping regions, simplifying the overall fabrication process while achieving high integration density through vertical transistor structures
Solution Approach 2:
The patent segments the transistor structure into distinct vertical components including semiconductor pillars, sidewall gates, and doping regions. This segmentation enables independent optimization of each component and simplifies the fabrication process by allowing sequential formation of each element
2Manufacturing precision
If doping implantation is performed to form source and drain regions, then the transistor functionality is achieved, but the positioning precision must be maintained
Solution Approach 1:
The patent introduces gates as an intermediary structure that serves as a mask during doping implantation. These sidewall gates precisely define the boundaries of source and drain regions, ensuring accurate doping positioning without requiring complex direct patterning methods
Solution Approach 2:
The patent transitions from planar gating to three-dimensional sidewall gating, where gates are formed on the vertical sidewalls of semiconductor pillars. This dimensional change enables precise spatial control of doping regions through the vertical dimension, achieving high positioning accuracy
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the accurate formation of vertical transistors with improved fabrication precision and performance, enhancing the integration density and efficiency of semiconductor memory devices.
Implementation Method 1
the upper and lower portions of the semiconductor pillars are doped using plasma doping
Implementation Method 2
performing implantation into the upper and lower portions of each of the semiconductor pillars where the gate is formed, with dopants of the opposite type from those in the semiconductor pillars
Implementation Method 3
After the upper and lower portions of the semiconductor pillars are doped with plasma doping, an annealing treatment is performed
Data Source
AI summary
The invention provides a semiconductor structure and a manufacturing method making the semiconductor structure. The method includes: providing a substrate; forming semiconductor pillars on the substrate; forming gate electrodes on the middle sidewalls of the semiconductor pillars; and performing dopant implantation to form source and drain regions. Since the gate-all-around (GAA) gates surrounding the semiconductor pillars are formed first, and the source region and the drain region are formed later by doping implantation, the precise position of the doping implantation can be ensured, thereby improving the fabrication accuracy of the semiconductor structure and improving the performance of the semiconductor structure.