Vertical PIN Diode Anode Contact Width Control
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Solution Overview
Problem
The existing manufacturing processes for vertical PIN diodes suffer from mechanical damage and residual deposits during the etching process, leading to high leakage currents, energy inefficiency, and reliability issues due to inaccurate control over the anode contact width and lateral surface damage.
Innovation Solution
A method involving the formation of an electrically insulating layer around the anode region, with a sacrificial side-guard ring to protect the anode area during etching, allowing for precise control over the anode contact width and minimizing mechanical damage, using ion implantation to create an electrically insulating layer and forming trenches in the insulating layer to expose the cathode region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a first dry etching self-aligned with the anode metallization is performed to form a trench, then the cathode contact can be formed in the trench, but mechanical damage and residual deposits are created on the lateral surfaces of the intrinsic layer, causing high leakage currents
Solution Approach 1:
An electrically insulating layer is formed around the anode region before the trench etching process. This preliminary action protects the intrinsic layer from mechanical damage and residual deposits during etching, preventing high leakage currents while still allowing the trench to be formed for cathode contact
Solution Approach 2:
The electrically insulating layer acts as an intermediary protective barrier between the etching process and the intrinsic layer. It prevents direct contact between the etching plasma and the semiconductor surfaces, eliminating mechanical damage and residual deposits that cause leakage currents
2Loss of energy
If the anode contact width is reduced to minimize parasitic capacitances, then energy efficiency improves, but manufacturing precision becomes difficult to control
Solution Approach 1:
The patent replaces mechanical alignment methods with a self-aligned process where the anode metallization itself defines the boundary for insulating layer formation. This substitution eliminates mechanical alignment errors and provides precise control over anode contact width, enabling minimization of parasitic capacitances while maintaining manufacturing precision
Solution Approach 2:
The anode metallization serves a dual function: as the electrical contact and as the alignment reference for forming the insulating layer. This self-service approach ensures that the anode contact width is precisely controlled by the metallization dimensions themselves, eliminating the need for separate alignment processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces leakage currents, enhances energy efficiency, and improves the reliability of vertical PIN diodes by maintaining the integrity of the anode contact and minimizing parasitic capacitances and resistances, while allowing for smaller anode contact dimensions and reduced surface recombination rates.
Implementation Method 1
forming an electrically insulating layer around the anode region, with a sacrificial side-guard ring to protect the anode area during etching, allowing for precise control over the anode contact width and minimizing mechanical damage, using ion implantation to create an electrically insulating layer
Data Source
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AI summary
The invention concerns a method of manufacturing a vertical PIN diode (30) comprising: providing an epitaxial wafer comprising a vertically stacked N-type layer (32), intrinsic layer (33) and P-type layer (34); forming an anode contact of the vertical PIN diode (30) by forming an anode metallization (35) on a first portion of the P-type layer defining an anode region (34a); forming an electrically insulating layer (36) around the anode region (34a) such that a first portion of the intrinsic layer (33) extends vertically between the N-type layer (32) and the anode region (34a) and second portions of the intrinsic layer (33) extend vertically between the N-type layer (32) and the electrically insulating layer (36); forming a trench (38) in the electrically insulating layer (36) and in the second portions of the intrinsic layer (33) so as to expose a portion of the N-type layer (32) defining a cathode region and to define a sacrificial side-guard ring (36a) consisting of a portion of the electrically insulating layer (36) that extends laterally between the trench (38) and the anode region (34a) and laterally surrounds said anode region (34a); and forming a cathode contact of the vertical PIN diode (30) by forming a cathode metallization (39) on the exposed portion of the N-type layer (32) defining the cathode region.