Vertical Pin Diode with Surface Electrodes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional vertical pin diodes are difficult to manufacture and cause radio wave interference due to conductive components within the substrate, making them unsuitable for solid-state plasma antennas.
Innovation Solution
A vertical pin diode design with a semiconductor substrate having P-type, intrinsic, and N-type regions stacked in a vertical direction, with electrodes on opposite surfaces and protection layers to prevent interference, along with waveguide and insulating layers to minimize radio wave interference and simplify manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal interconnections are disposed under trenches formed in the substrate to create a vertical pin diode, then the diode structure is formed, but the manufacturing process becomes complicated and radio wave interference occurs
Solution Approach 1:
The patent removes metal interconnections from the substrate interior by forming the anode and cathode electrodes on opposite surfaces of the substrate. This extraction eliminates the harmful metal interconnections that caused radio wave interference while maintaining the vertical pin diode structure functionality.
Solution Approach 2:
The patent transitions from a three-dimensional structure with metal interconnections embedded within the substrate to a two-dimensional surface-mounted electrode configuration. By placing electrodes on opposite surfaces and using conductive regions within the semiconductor layers themselves, the design eliminates the need for internal metal interconnections and complex trench structures.
2Reliability
If connection regions pass through intrinsic regions to connect electrodes, then electrical connection is achieved, but radio wave interference is caused and manufacturing becomes difficult
Solution Approach 1:
The patent creates localized conductive regions (P-type and N-type doped regions) within the semiconductor layers that provide electrical connection pathways without requiring metal interconnections to pass through the intrinsic region. The conductive regions are strategically positioned to maintain electrical functionality while preserving the intrinsic region's radio wave transparency.
3Reliability
If a vertical pin diode structure is implemented, then uniform charge dispersion in the intrinsic region is achieved, but manufacturing complexity and radio wave interference increase
Solution Approach 1:
The patent segments the diode structure into distinct functional layers (P-type region, intrinsic region, N-type region) with electrodes on opposite surfaces. This segmentation allows the intrinsic region to maintain its uniform charge dispersion property while eliminating the need for complex internal metal interconnections that would disrupt this uniformity and cause radio wave interference.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design allows for easy manufacturing and reduces radio wave interference, enabling efficient signal transmission and reconfigurable antenna applications without conductive components inside the substrate.
Implementation Method 1
a P-type region, an intrinsic region, and an N-type region are sequentially disposed in a vertical direction to be formed in a semiconductor substrate
Implementation Method 2
an electrical or optical stimulus is applied to a desired region of a semiconductor substrate, which is normally in a dielectric state, for a desired period of time so that the semiconductor substrate is changed to be in a conductive state
Data Source
AI summary
A vertical positive-intrinsic-negative (pin) diode includes a semiconductor substrate in which a P-type region, an intrinsic region, and an N-type region are sequentially disposed in a vertical direction to be formed therein, a first electrode formed on one surface of the semiconductor substrate to be in electrical contact with the P-type region, and a second electrode formed on the other surface of the semiconductor substrate to be in electrical contact with the N-type region, wherein the P-type region and the N-type region are respectively disposed in an upper portion and a lower portion of the semiconductor substrate to be opposite to each other.