Density-Conforming Vertical Plate Capacitors with Via Bars
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Solution Overview
Problem
Existing vertical plate capacitors face limitations in capacitance due to the thickness of interconnects and variations in metal density, which affect device performance and yield, especially in high-density circuit designs, leading to issues like electrical shorting and resistance variations.
Innovation Solution
The use of via bars with a width and length greater than the width, which electrically couple interconnects and contribute significantly to the capacitance, allowing for a density-conforming design that enhances capacitance without increasing interconnect length or height, and improves metal height uniformity through optimized chemical mechanical planarization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the dimensions of vertical plate capacitor are increased to increase charge storage, then capacitance is improved, but device density is worsened due to larger chip area occupation
Solution Approach 1:
The patent transitions from planar capacitor design to three-dimensional vertical plate structure. Multiple electrode sets are stacked vertically with vias coupling adjacent sets, creating a vertical extension that increases capacitance without proportionally increasing chip area. The via bars further extend the conductive path vertically, maximizing charge storage within a compact footprint.
2Quantity of substance
If the interconnect length is increased to achieve high capacitance, then capacitance is improved, but metal density variations are worsened
Solution Approach 1:
The capacitor structure is divided into multiple discrete electrode sets (typically 5-8 layers) stacked vertically. Each electrode set contains interconnects that can be independently formed and controlled. This segmentation allows each layer's metal density to be managed separately, reducing cumulative variations while achieving high overall capacitance through the stacked configuration.
Solution Approach 2:
The patent applies different metal density characteristics to different regions: the capacitor region uses optimized interconnect lengths and via bar dimensions for maximum capacitance, while surrounding circuit regions maintain standard metal densities. This local optimization allows high capacitance in the capacitor region without forcing uniform high metal density across the entire chip, thereby maintaining CMP processability and reducing metal height variations.
3Quantity of substance
If the number of via holes is increased to couple stacked electrode sets, then capacitance is improved, but manufacturing complexity is worsened
Solution Approach 1:
Adjacent vias are merged into continuous via bars that extend through multiple dielectric layers. Instead of forming and filling individual via holes separately, the via bars are formed as continuous structures using damascene processes. This merging reduces the number of discrete via formation steps, simplifies the fabrication process, and simultaneously increases capacitance by providing extended conductive paths between electrode sets.
4Manufacturing precision
If CMP is optimized for high metal density regions, then metal height uniformity is improved, but capacitor capacitance is worsened due to overpolishing
Solution Approach 1:
The patent designs the capacitor structure with local quality variations: via bars have greater length than width to provide extended capacitance contribution, and interconnects in the capacitor region are optimized for maximum overlap area. These local optimizations ensure that even with CMP planarization, the capacitor region maintains sufficient metal height and capacitance, while the overall metal height uniformity across the chip is improved by the density-conforming design.
Data Source
AI summary
Density-conforming vertical plate capacitors exhibiting enhanced capacitance and methods for fabricating density-conforming vertical plate capacitors exhibiting enhanced capacitance are provided. An embodiment of the density-conforming vertical plate capacitor comprises a first conductive interconnect and a second conductive interconnect. The second conductive interconnect overlies the first conductive interconnect and is substantially aligned with the first conductive interconnect. A via bar electrically couples the first conductive interconnect and the second conductive interconnect. The via bar has a width and a length that is larger than the width and contributes to the capacitance of the vertical plate capacitor.