Vertical PMIC Package Layout for Shorter Power Paths
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Solution Overview
Problem
Increasing power consumption and limited size in electronic device packages due to longer electrical paths and increased circuit footprint on substrates, necessitating improvements in packaging.
Innovation Solution
A vertical electrical connection using a power management integrated circuit (PMIC) with double-sided terminals and integrated passive elements, such as inductors and capacitors, to reduce the substrate area and enhance power stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a longer electrical path is used for power signal transmission, then the PMIC can be positioned flexibly on the substrate, but the power consumption increases
Solution Approach 1:
The patent transitions from a planar (2D) electrical path to a three-dimensional (3D) vertical path by routing power signals through vias that penetrate the substrate. This dimensional change allows the PMIC to be positioned on one surface while maintaining short electrical connections to components on the opposite surface, eliminating the need for long lateral traces and reducing power consumption accordingly.
2Ease of operation
If a longer electrical path is used for power signal transmission, then the PMIC can be positioned flexibly on the substrate, but the power signal path length increases
Solution Approach 1:
The patent transitions from a planar (2D) electrical path to a three-dimensional (3D) vertical path by routing power signals through vias that penetrate the substrate. This dimensional change allows the PMIC to be positioned on one surface while maintaining short electrical connections to components on the opposite surface, eliminating the need for long lateral traces and reducing power consumption accordingly.
3Reliability
If integrated passive elements are added to the PMIC, then power stability is enhanced, but device complexity increases
Solution Approach 1:
The patent integrates passive elements (inductors, capacitors, resistors) directly into the PMIC structure, merging previously separate components into a single integrated unit. This consolidation enhances power stability by minimizing parasitic effects and improving signal integrity, while the systematic integration approach manages complexity through unified design and fabrication processes.
4Device complexity
If traditional separate component layout is used, then device complexity is lower, but substrate area increases
Solution Approach 1:
The patent integrates passive elements (inductors, capacitors, resistors) directly into the PMIC structure, merging previously separate components into a single integrated unit. This consolidation enhances power stability by minimizing parasitic effects and improving signal integrity, while the systematic integration approach manages complexity through unified design and fabrication processes.
Solution Approach 2:
The patent embeds passive elements within the PMIC structure and utilizes vertical stacking arrangements where components are positioned in three-dimensional space rather than spreading laterally. This nesting approach allows multiple functional elements to coexist in a compact footprint, dramatically reducing the required substrate area while maintaining all necessary functionality.
Data Source
AI summary
The present disclosure relates to an electronic device package that includes a first substrate, a second substrate over the first substrate, and an integrated circuit (IC) connected between the first substrate and the second substrate. The IC is configured to regulate a power signal, wherein a projection of a power signal path between the IC and the second substrate on the first substrate is entirely within a projection of the IC on the first substrate.