Vertical PMOS Transistor With Strained Si-Ge Layers
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Solution Overview
Problem
Current PMOS transistors occupy most of the surface area of the substrate due to their planar configuration, limiting the increase in semiconductor element density and transistor performance when size reduction is attempted without advanced manufacturing processes.
Innovation Solution
A vertical PMOS field effect transistor design featuring a substrate with a strained Si—Ge layer structure, including a mesa structure with epitaxial Si layers and nitride layers, which reduces lateral unit area and increases element density by vertically disposing the drain, gate, and source, and applying stress to enhance hole mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a planar PMOS configuration is used, then the transistor structure is simple and easy to manufacture, but the lateral unit area is large which limits element density
Solution Approach 1:
The patent transitions from a planar two-dimensional configuration to a vertical three-dimensional configuration. The source, drain, and gate are arranged vertically along the depth direction rather than laterally in a plane. This dimensional change reduces the lateral footprint while maintaining the essential transistor functionality, thereby increasing element density without significantly complicating the manufacturing process.
2Area of stationary object
If the transistor size is reduced to increase element density, then the lateral unit area is reduced, but the performance cannot be enhanced without advanced manufacturing processes
Solution Approach 1:
The patent employs a composite material structure consisting of multiple layers including strained Si-Ge layers, epitaxial Si layers, and nitride layers. This composite structure provides both mechanical stress to enhance carrier mobility and electrical functionality. The strained Si-Ge layers specifically introduce stress to improve hole mobility in the channel, thereby maintaining or enhancing transistor performance despite the reduced size.
Solution Approach 2:
The patent applies different material properties and stress conditions to specific local regions. The strained Si-Ge layers are positioned specifically to apply stress to the channel region where carrier flow occurs, while other regions maintain their original structure. This localized application of stress and material variation enhances performance in critical areas without requiring advanced manufacturing across the entire device.
3Area of stationary object
If the element density is increased by reducing transistor size, then more transistors can be integrated, but the transport speed of carriers may be reduced
Solution Approach 1:
The patent changes the physical parameters of the materials used in the transistor structure. By introducing strained Si-Ge layers with different lattice constants, mechanical stress is applied to the channel region. This stress modifies the band structure and increases carrier mobility, thereby maintaining high transport speed even in smaller, densely packed transistors. The epitaxial growth parameters are also optimized to control layer thickness and stress distribution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The vertical configuration reduces the lateral unit area, increases semiconductor element density, and enhances transistor performance by increasing hole mobility through vertical stress forces applied by the strained Si—Ge layers.
Implementation Method 1
The first strained Si—Ge layer and the second strained Si—Ge layer provides a vertical stress force to the epitaxial Si layer to increase the hole mobility
Data Source
AI summary
A PMOS field effect transistor includes a substrate, a first nitride layer, a mesa structure, two gate oxide films, a gate stack layer and a second nitride layer. The substrate has a oxide layer and a first doping area. The first nitride layer is located on the oxide layer. The mesa structure includes a first strained Si—Ge layer, an epitaxial Si layer and a second strained Si—Ge layer. The first strained Si—Ge layer is located on the oxide layer and the first nitride layer. The epitaxial Si layer is located on the first strained Si—Ge layer. The second strained Si—Ge layer is located on the epitaxial Si layer. In the surface layer of the second strained Si—Ge layer, there is a second doping area. The two gate oxide films are located at two sides of the mesa structure.