Vertical PN Junction Modulators with Backside Contacts
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Solution Overview
Problem
Conventional semiconductor fabrication processes face challenges in scaling to sub-10 nanometer nodes due to variability and constraints on multi-gate transistor dimensions, leading to space inefficiency and increased resistance in PN junctions.
Innovation Solution
The implementation of vertically oriented PN junctions with dual-sided processing allows for backside contacts, reducing real estate usage and improving electrical performance by enabling lower contact resistance and efficient integration of photonics modulators with optical waveguides.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional horizontal PN junctions are used in scaled multi-gate transistors, then device density increases, but contact resistance increases and electrical performance deteriorates
Solution Approach 1:
The patent transitions from conventional horizontal PN junctions to vertical PN junctions, changing the spatial orientation from in-plane to out-of-plane. This dimensional change allows current to flow vertically through the junction, reducing the effective path length and contact resistance while maintaining high device density in the scaled multi-gate transistor structure
Solution Approach 2:
The patent inverts the traditional horizontal arrangement of PN junctions by stacking them vertically. This inversion places the P-type and N-type regions in vertical succession rather than lateral adjacency, fundamentally changing the current flow path and reducing the resistance encountered by charge carriers
2Productivity
If feature size is reduced to increase device density, then more devices fit on chip, but fabrication variability increases and process constraints become overwhelming
Solution Approach 1:
By moving to vertical PN junctions, the patent reduces the lateral footprint of each device, allowing higher density without proportionally reducing feature sizes. The vertical stacking enables compact integration while maintaining larger, more controllable lateral dimensions that are easier to fabricate with precision
3Quantity of substance
If multi-gate transistor dimensions are reduced to increase capacity, then chip capacity increases, but space constraints and process limitations become overwhelming
Solution Approach 1:
The vertical orientation of PN junctions enables three-dimensional integration within the multi-gate transistor structure, increasing functional capacity without proportionally increasing lateral device dimensions. This reduces the number of devices required per unit area, thereby reducing overall process complexity and constraints
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the scalability of semiconductor devices by optimizing space usage and electrical performance, facilitating the integration of photonics modulators with reduced resistance and increased efficiency.
Implementation Method 1
photonics modulators with backside contacts
Data Source
AI summary
Embodiments disclosed herein include a photonics module and methods of forming photonics modules. In an embodiment, the photonics module comprises a waveguide, and a modulator adjacent to the waveguide. In an embodiment, the modulator comprises a PN junction with a P-doped region and an N-doped region, where the PN junction is vertically oriented so that the P-doped region is over the N-doped region.