Vertical PN Source/Drain Connection in Stacked Nanosheet FETs
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Solution Overview
Problem
The complexity of manufacturing multi-stack semiconductor devices increases due to the need for multiple connections between lower and upper stack field-effect transistors, which complicates the structure and process, and results in increased device size and reduced device density.
Innovation Solution
A multi-stack semiconductor device with a stepped nanosheet structure having different channel region widths between nanosheet layers, where the 4th source/drain region is directly connected to the 2nd source/drain region forming a PN junction, and using a connection structure of metal, metal compound, or silicon for ohmic contact, simplifying the manufacturing process and enhancing device density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple connection structures are used to connect lower and upper stack field-effect transistors to power sources and circuit elements, then the multi-stack semiconductor device can be completed with proper electrical connections, but the structure becomes more complicated and device density is reduced
Solution Approach 1:
The patent merges the connection structures between lower and upper stack field-effect transistors by forming a combined connection region that integrates multiple electrical connections into a single unified structure. This reduces the number of separate contact structures needed while maintaining all necessary electrical connections to power sources and circuit elements, thereby simplifying the overall device structure without compromising connection completeness
Solution Approach 2:
The connection structure is designed to serve multiple functions simultaneously: it provides electrical connections to different power sources (VDD, VSS), connects to circuit elements, and enables signal transmission between stacked transistors. This multi-functional design eliminates the need for separate dedicated connection structures for each function, reducing structural complexity while ensuring reliable electrical connectivity
2Reliability
If multiple connection structures are used to connect lower and upper stack field-effect transistors, then proper electrical connections are achieved, but the number of contact structures increases and device density decreases
Solution Approach 1:
Multiple separate contact structures are merged into a single integrated connection region that provides all necessary electrical connections. Instead of having distinct contact structures for each power source and circuit element connection, the patent combines these into one unified structure, thereby reducing the total number of contact structures while maintaining complete electrical connectivity
Solution Approach 2:
The connection structure is designed as a multi-functional element that simultaneously provides multiple electrical connections to different power sources and circuit elements. This single structure performs the work of what would traditionally require multiple separate contacts, reducing the quantity of contact structures needed in the device
3Reliability
If conventional connection structures are used in multi-stack semiconductor devices, then electrical connections are established, but the manufacturing process becomes more complicated
Solution Approach 1:
The manufacturing process is simplified by merging multiple connection formation steps into a single integrated process. Instead of separately forming multiple contact structures at different stages, the patent combines these into one connection formation step that creates all necessary electrical connections simultaneously, reducing manufacturing complexity while ensuring proper electrical connectivity
Solution Approach 2:
The connection structure is designed and formed in advance during the semiconductor device fabrication process, integrating the connection formation with the transistor stacking process. This preliminary integration of connection structures with the main device fabrication eliminates the need for subsequent separate connection formation steps, simplifying the overall manufacturing process while ensuring electrical connections are properly established
Data Source
Figure 1A
Figure 1B~1C
Figure 1D
AI summary
A multi-stack semiconductor device includes: a substrate (300); a lower field-effect transistor (310) including a lower channel structure, a lower gate structure (311) surrounding the lower channel structure, and 1st and 2nd source/drain regions (313, 314); and an upper field-effect transistor (311), on the lower field-effect transistor, including an upper channel structure, an upper gate structure (321) surrounding the upper channel structure, and 3rd and 4th source/drain regions (323, 324) vertically above the 1st and 2nd source/drain regions, respectively, wherein the 1st source/drain region is connected to one of a positive voltage source and a negative voltage source, and the 3rd source/drain region is connected to the other of the positive voltage source and the negative voltage source, and wherein a top portion of the 2nd source/drain region (314) and a bottom portion the 4th source/drain region (324) are connected to each other.