Vertical Parasitic PNP Transistor Deep-Hole Collector Contact
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Solution Overview
Problem
In BiCMOS processes, vertical parasitic PNP transistors have a large device area and high collector resistance due to the conventional method of picking up the collector through an adjacent active region, limiting further size reduction and performance enhancement.
Innovation Solution
A vertical parasitic PNP transistor is designed with a collector region deeper than shallow trench isolations, pseudo buried layers extending laterally to contact the collector, and a base region with an N-type ion implantation, along with an emitter region using a P-type Silicon-Germanium epitaxial layer, all connected via deep-hole contacts and metal contacts, reducing device area and collector resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the collector is picked up through another active region adjacent to the collector region, then the device structure is determined by vertical characteristics, but the device area becomes large and connecting resistance increases
Solution Approach 1:
The patent transitions from a planar collection structure to a vertical three-dimensional structure by forming a deep-hole contact that extends through the STI layer down to the collector region. This vertical dimensionality change allows the collector electrode to be directly connected beneath the active region without requiring lateral extension into adjacent areas, thereby reducing device footprint while maintaining electrical connectivity.
Solution Approach 2:
The deep-hole contact structure nests within the STI isolation region, utilizing the vertical space beneath the isolation layer to route the collector connection. This nesting approach allows the collector electrode to be positioned directly under the active region, eliminating the need for lateral expansion into adjacent active regions and reducing overall device area.
2Reliability
If the collector is picked up through another active region adjacent to the collector region, then the vertical structure is maintained, but the connecting resistance of the collector becomes large
Solution Approach 1:
The patent reduces collector resistance by creating a vertical conduction path through the deep-hole contact that directly reaches the collector region. This vertical pathway shortens the current transport distance compared to lateral connections through adjacent active regions, thereby reducing ohmic losses and improving electrical performance while preserving the vertical device architecture.
Solution Approach 2:
The STI isolation layer serves as an intermediary medium that is selectively removed or penetrated to form the deep-hole contact. This allows the collector electrode to be directly connected to the collector region through a dedicated vertical pathway, bypassing the high-resistance lateral paths through adjacent active regions while maintaining the isolation function in other areas.
3Ease of manufacture
If the collector is picked up through another active region, then the device structure is established, but further reduction of device size is greatly limited
Solution Approach 1:
The patent overcomes the lateral size limitation by exploiting the vertical dimension. The deep-hole contact extends downward through the STI layer to reach the collector region, allowing the device to maintain a compact lateral footprint while establishing proper electrical connections through the vertical axis. This enables further miniaturization in the planar direction without compromising structural integrity or electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution results in higher current amplification and frequency characteristics, providing a compact and high-performance output device for high-speed BiCMOS circuits while maintaining current gain and reducing manufacturing costs.
Implementation Method 1
a collector region, comprising a P-type ion implantation region formed in the active region
Implementation Method 2
pseudo buried layers, comprising P-type ion implantation regions formed at the bottom of the shallow trench isolations
Implementation Method 3
a base region, comprising an N-type ion implantation region formed on the collector region
Implementation Method 4
an emitter region, comprising a P-type Silicon-Germanium epitaxial layer formed on the base region
Data Source
AI summary
The invention discloses a vertical parasitic PNP transistor in a BiCMOS process and manufacturing method of the same, wherein an active region is isolated by STIs. The transistor includes a collector region, a base region, an emitter region, pseudo buried layers, and N-type polysilicon. The pseudo buried layers, formed at the bottom of the STIs located on both sides of the collector region, extend laterally into the active region and contact with the collector region, whose electrodes are picked up through making deep-hole contacts in the STIs. The N-type polysilicon is formed on the base region and contacts with it, whose electrodes are picked up through making metal contacts on the N-type polysilicon. The transistors can be used as output devices in high-speed and high-gain circuits, efficiently reducing the transistors area, diminishing the collector resistance, and improving the transistors performance. The method can reduce the cost without additional technological conditions.