3D Capacitor Layout in Vertical Power Supply Boards
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Solution Overview
Problem
Conventional vertical power supply systems face challenges in reducing transmission impedance and improving dynamic performance due to limited output capacitors, which are embedded in the substrate, leading to increased substrate size, manufacturing issues, and mismatch stress from different thermal expansion coefficients.
Innovation Solution
The capacitors are disposed on the surface of the system board and substrate, and/or the side walls of conductive portions, allowing for a three-dimensional arrangement that increases the number of capacitors and improves total capacitance, using a wider range of materials at lower costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If output capacitors are embedded in the substrate, then the connection impedance between power unit and processor chip is reduced, but the substrate area increases and manufacturing complexity increases
Solution Approach 1:
The patent transitions from two-dimensional planar embedding of capacitors within the substrate to three-dimensional surface mounting on both sides of the substrate. This dimensional change allows capacitors to be arranged vertically on the substrate surfaces rather than being constrained to a single plane, thereby reducing the required substrate area while maintaining or increasing the total capacitor capacity.
Solution Approach 2:
The patent divides the capacitor arrangement into multiple groups located on different surfaces and regions of the substrate. By segmenting the capacitor placement across front and back surfaces, and potentially across multiple substrate layers, the design achieves better spatial distribution and reduces the footprint required on any single surface.
2Reliability
If more output capacitors are embedded in the substrate, then the equivalent series resistance and equivalent series inductance decrease, but the substrate becomes more prone to bending and manufacturing issues arise
Solution Approach 1:
By moving capacitor mounting from internal embedding to external surface placement, the patent eliminates the need for complex through-substrate vias and internal routing structures that weaken the substrate. Surface-mounted capacitors attach to external pads, preserving substrate structural integrity while achieving the required capacitance values for low ESR and ESL.
Solution Approach 2:
The patent extracts the capacitors from the substrate interior and relocates them to the substrate surface. This extraction removes the capacitors from the substrate's structural path, eliminating the mechanical stress and bending issues caused by embedding large numbers of capacitors within the substrate thickness.
3Reliability
If output capacitors are embedded in the substrate, then the connection impedance is reduced, but different thermal expansion coefficients cause mismatch stress
Solution Approach 1:
By removing capacitors from the substrate interior and placing them on external surfaces, the patent eliminates direct thermal coupling between capacitors and substrate through thick vias and solder joints. Surface-mounted capacitors experience thermal cycles more independently, reducing differential thermal expansion stress at the capacitor-substrate interface.
4Ease of manufacture
If output capacitors are arranged on a two-dimensional plane, then the layout is simple, but the quantity of capacitors per unit area is limited
Solution Approach 1:
The patent utilizes both front and back surfaces of the substrate for capacitor placement, effectively creating a two-layer two-dimensional arrangement. This approach doubles the available surface area for capacitor mounting compared to single-sided placement, thereby increasing the total number of capacitors that can be installed without adding substrate area.
Data Source
AI summary
A vertical power supply system and a manufacturing method of a connection board are provided. The vertical power supply system includes a system board, a substrate, a chip unit, a plurality of first capacitors, a plurality of second capacitors, a plurality of conductive portions and a power unit. The system board includes a first surface and a second surface which are opposite to each other. The substrate includes a third surface and a fourth surface which are opposite to each other, and the third surface is located between the fourth surface and the second surface. The chip unit is disposed on the first surface. The first capacitors are disposed on the second surface. The second capacitors are disposed on the third surface. The third surface and the second surface are electrically connected through the conductive portions. The power unit is disposed on the fourth surface.