Vertical Multi-Stage Power Delivery for Dense Chip Arrays

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Solution Overview

Problem

Existing computing systems face challenges in achieving high computing density due to limited area for associated electronics, and inefficient power delivery impacts system performance.

Innovation Solution

A computing system with an array of chips and vertically integrated power conversion paths, including multiple power conversion stages on stacked printed circuit boards, which convert high voltage, low current input signals to low voltage, high current output signals, reducing power losses and enabling high compute density.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If power delivery is implemented using conventional horizontal routing, then system performance is maintained, but resistive losses and parasitic inductance increase, reducing power delivery efficiency

Engineering Contradiction:
Improveresistive lossesVSAvoidpower delivery structure
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent transitions from conventional horizontal power routing to vertical power delivery by stacking power conversion stages and chips in three-dimensional space. This dimensional change reduces the length of power delivery paths, thereby minimizing resistive losses and parasitic inductance while improving overall power delivery efficiency

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If computing density is increased by adding more chips, then system computational capacity improves, but available area for associated electronics is reduced

Engineering Contradiction:
Improvecomputing densityVSAvoidarea for electronics
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

The patent employs vertical stacking of multiple chips and power conversion stages along the z-axis, transforming a two-dimensional layout into a three-dimensional structure. This enables higher computing density by utilizing vertical space rather than consuming additional horizontal area, allowing more chips to be integrated within the same footprint

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent integrates power conversion stages and chips in a nested vertical configuration where multiple functional components are stacked one above another. Each chip is paired with its dedicated power conversion stage in a compact nested arrangement, maximizing space utilization and enabling high computing density without increasing the overall system footprint

Inventive Principle:
Principle #7Nested doll (Nesting)

3Loss of energy

If multiple power conversion stages are vertically integrated, then power delivery efficiency improves, but manufacturing complexity increases

Engineering Contradiction:
Improvepower lossesVSAvoidassembly process
Core Design Contradiction:
Loss of energyVSEase of manufacture

Solution Approach 1:

The patent divides the power conversion function into multiple discrete stages, each implemented as a separate module that can be independently manufactured and tested. These segmented power conversion stages are then vertically stacked and interconnected, allowing for modular assembly that simplifies the overall manufacturing process while maintaining the efficiency benefits of multi-stage conversion

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The vertical power delivery system reduces resistive losses and parasitic inductance, allowing for high computing density and efficient power supply to chips, suitable for applications like neural network training and machine learning.

Implementation Method 1

The plurality of power conversion paths includes a first power conversion path. The first power conversion path includes a first power conversion stage and a second power conversion stage configured to receive a power supply signal from the first power conversion stage, generate an output power supply signal having a lower voltage and a higher current than the power supply signal

Methodology Applied
Scientific EffectElectromagnetic conversion: Electromagnetic Induction

Implementation Method 2

The first power supply module can include a thermal transfer structure positioned between the first power conversion stage and the second power conversion stage

Methodology Applied
Scientific EffectThermal transfer: Heat Exchanger

Data Source

PatentUS12554302B2Multi-stage array based vertically integrated power delivery
Publication Date: 2026.02.17 TESLA INC
  • US12554302B2 patent drawing
  • US12554302B2 patent drawing
  • US12554302B2 patent drawing

AI summary

Aspects of this disclosure relate to power delivery to chips in an array. An array of power conversion paths can be positioned vertically relative to the chips of the array. A power conversion path can convert a high voltage, low current signal to a low voltage, high current. The power conversion path can include a first power conversion stage and a second power conversion stage. The power conversion path can be implemented in a power supply module, for example.