Vertical Power Gate Circuits for Semiconductor Area Reduction
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Solution Overview
Problem
The increasing demand for smaller electronic products with higher density integrated circuits poses a challenge in reducing the size of power gate circuits, which are typically large and consume significant area on semiconductor dies, while also needing to manage power consumption effectively in battery-operated devices.
Innovation Solution
The use of vertically oriented p-channel and n-channel transistors in power gate circuits, which are activated or deactivated based on control signals to provide power only when necessary, reducing power consumption and minimizing circuit area by using conductive structures that extend along the length of the power gate circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If power gate circuits are designed to carry sufficient power to various circuits when activated, then power delivery capability is improved, but circuit area increases significantly
Solution Approach 1:
The patent transitions from planar transistor layout to vertically stacked three-dimensional transistor structures. Multiple transistor layers are stacked vertically between common source and drain regions, enabling higher power delivery capability through increased transistor count without proportionally increasing the lateral circuit area. This vertical stacking approach directly resolves the contradiction by adding power capacity in the vertical dimension rather than expanding horizontally.
2Power
If power gate circuits are made larger to carry sufficient power, then power delivery capability is improved, but density of integrated circuits decreases
Solution Approach 1:
By stacking transistors vertically in multiple layers between common source and drain regions, the patent achieves higher power delivery capability within a compact lateral footprint. This vertical stacking enables more functional blocks to be integrated on the same die area, thereby maintaining or improving circuit density while providing sufficient power delivery capacity for each block.
3Use of energy by stationary object
If conventional power gate circuits are used, then power consumption control is achieved, but circuit area remains large
Solution Approach 1:
The patent employs vertically stacked transistor structures that provide the necessary power delivery capability in a compact three-dimensional configuration. This approach maintains effective power consumption control by enabling selective activation of functional blocks while significantly reducing the lateral area occupied by power gate circuits compared to conventional planar designs.
Solution Approach 2:
Multiple transistor layers are merged and stacked vertically to form a unified power gate structure. This consolidation achieves the required power delivery capability through the combined effect of stacked transistors sharing common source and drain regions, thereby reducing the overall circuit area compared to using separate planar transistor structures for each power delivery path.
Data Source
AI summary
Apparatuses and methods for gate power to circuits of semiconductor devices are described. An example apparatus includes a substrate, a first wiring and a second wiring, and a plurality of transistors. The first wiring may be supplied with a power voltage, and the first wiring is formed over the substrate and is elongating in a first direction. The second wiring may be formed between the substrate and the first wiring, and vertically overlapping the first wiring with the second wiring elongating in the first direction. The plurality of transistors are vertically coupled between the first wiring and the second wiring.