Vertical Power Gate Layout for Backside Power Delivery Scaling
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Solution Overview
Problem
The scaling of multi-gate transistors in integrated circuits poses challenges in maintaining mobility and short channel control, particularly as dimensions approach the 10 nanometer node, and conventional power delivery methods lead to increased power network resistance and signal routing issues.
Innovation Solution
The implementation of vertical gate-all-around transistors and backside power delivery, where power is delivered through a vertical keeper or power gate on the backside of the substrate, reducing the need for wide metal wires on the front side and allowing for more aggressive scaling and improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional power delivery methods are used through front-side metal wires, then power can be delivered to transistors, but power network resistance increases and scaling becomes limited
Solution Approach 1:
The patent inverts the conventional power delivery approach by delivering power from the backside of the substrate through vertical keeper or power gate structures, rather than through front-side metal wires. This inversion eliminates the need for wide metal wires on the front side, reduces power network resistance, and enables more aggressive scaling of transistor dimensions to below the 10 nanometer node.
Solution Approach 2:
The patent transitions from two-dimensional front-side power delivery through metal wires to three-dimensional backside power delivery through vertical structures. By utilizing the vertical dimension and backside access, the patent achieves lower resistance power delivery and frees up front-side real estate for increased device density and scaling.
2Reliability
If transistor dimensions are scaled down to maintain mobility and short channel control, then device performance improves, but lithographic constraints become overwhelming
Solution Approach 1:
The patent inverts the conventional approach by accessing power delivery from the backside rather than through front-side lithographic patterns. This eliminates the need for complex lithographic processes to create wide metal wires and spacing, enabling scaling below the 10 nanometer node without overwhelming lithographic constraints.
3Reliability
If wide metal wires are used on the front side for power delivery, then power network resistance is reduced, but integration density decreases
Solution Approach 1:
The patent extracts the power delivery function from the front-side metal wire network and relocates it to backside vertical keeper or power gate structures. This extraction eliminates the need for wide metal wires on the front side, freeing up area for increased device density while maintaining low power network resistance through the vertical power delivery path.
Solution Approach 2:
The patent moves power delivery from the two-dimensional front-side plane to the three-dimensional backside vertical structures. This dimensional change allows power delivery without consuming front-side area, enabling both low resistance and high integration density.
Data Source
AI summary
Structures having vertical keeper or power gate for backside power delivery are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of fin-based transistors, and a plurality of metallization layers above the fin-based transistors of the device layer. A backside structure is below the fin-based transistors of the device layer. The backside structure includes a ground metal line. One or more vertical gate all-around transistors is between the fin-based transistors of the device layer and the ground metal line of the backside structure.