Vertical Power Rail for Semiconductor Standard Cells
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Solution Overview
Problem
Conventional power rail structures in semiconductor integrated circuits face challenges due to high resistance in metal lines, leading to increased metal resource usage, die size, and reduced product frequency, primarily caused by small cross-sectional areas, edge scattering, and the presence of liners, which also result in inefficient multi-level conductor connections and bulk conductor material loss.
Innovation Solution
The implementation of a power rail structure that includes a vertical section of conductive material extending continuously through multiple vertical levels of a stack, reducing the need for dense vias and high-resistance liners, thereby achieving a resistance equal to the bulk resistance of the conductive material, and allowing for increased geometric size and efficient signal routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional multi-level metal power rails with vias are used, then power can be supplied to standard cells, but the resistance is high due to small cross-sectional area, edge scattering, and liners
Solution Approach 1:
The patent transitions from planar power rails to a vertical 3D configuration by forming a power rail that extends through multiple metal layers (M0, M1, M2) using a single continuous conductive path. This vertical dimensionality change increases the effective cross-sectional area for current flow while eliminating via connections, thereby reducing resistance without requiring higher manufacturing precision in traditional via formation
Solution Approach 2:
The patent merges multiple discrete power rail segments across different metal layers into a single continuous power rail structure. By combining the power rail functions of M0, M1, and M2 layers into one unified conductive path, it eliminates the need for separate vias and liner interfaces, reducing total resistance through the removal of multiple high-resistance connection points
2Reliability
If more metal resources are allocated to power grids to reduce resistance, then power supply improves, but die size increases due to fewer available signal routing tracks
Solution Approach 1:
The patent utilizes the vertical dimension by extending the power rail through multiple metal layers (M0, M1, M2) to increase the effective conductive cross-section. This approach reduces power rail resistance without consuming additional lateral die area, as the resistance reduction is achieved through vertical stacking rather than lateral expansion, thereby preserving signal routing tracks
Solution Approach 2:
The patent creates a composite power rail structure that integrates conductive material across multiple metal layers with different insulating layers. This composite construction effectively increases the total conductive cross-sectional area available for power transport without increasing the lateral footprint, allowing reduced resistance while maintaining compact die size and available routing space
3Ease of manufacture
If multiple discrete levels of conductors connected by vias are used, then power distribution is achieved, but fabrication becomes increasingly challenging due to high resistance
Solution Approach 1:
The patent merges the formation of power rails across multiple metal layers into a single fabrication process step. By patternning and forming the power rail continuously through M0, M1, and M2 layers without requiring separate via formation and filling steps, it simplifies manufacturing while eliminating the high resistance associated with multiple via connections and liner interfaces
Solution Approach 2:
The patent extracts and eliminates the via connection elements from the power rail structure. By removing the need for vias to connect discrete metal layer segments, it eliminates the associated fabrication complexity and high resistance problems, achieving direct continuous conductor paths through the metal layers without intermediate connection points
4Strength
If barriers and liners are present at each dual-damascene level, then conductor protection is provided, but rail dimensions are narrowed and bulk conductor material loss increases
Solution Approach 1:
The patent merges the power rail formation into a single continuous structure that eliminates the need for multiple dual-damascene processing steps. This consolidation removes the requirement for repeated barrier and liner depositions at each metal layer interface, reducing total liner material that would otherwise consume valuable conductor space and increase effective resistance
Solution Approach 2:
The patent extracts and eliminates the barrier and liner layers from the power rail structure by using a single continuous formation process. By removing these protective layers that are unnecessary in the continuous power rail design, it recovers lost conductor cross-sectional area and reduces bulk conductor material loss, allowing larger effective rail dimensions
Data Source
AI summary
A semiconductor integrated circuit including a substrate, a series of metal layers, and a series of insulating layers. The metal layers and the insulating layers are alternately arranged in a stack on the substrate. The semiconductor integrated circuit also includes at least two standard cells in the substrate and at least one power rail crossing over boundaries of the at least two standard cells. The power rail includes a vertical section of conductive material extending continuously through at least two vertical levels of the stack. The two vertical levels of the stack include one metal layer and one insulating layer. The insulating layer is above the metal layer.