Vertical Power Semiconductor Layout for Surge Current Reliability
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Solution Overview
Problem
The development of new generations of vertical power semiconductor devices faces challenges in optimizing device geometries to enhance functionalities per unit area while ensuring reliability and cost-effectiveness, particularly in the design of edge termination areas.
Innovation Solution
A vertical power semiconductor device design that includes a semiconductor body with a transistor cell area, an edge termination area, a gate line area, and a source or emitter line area, featuring a termination structure and transistor cells, which improves current distribution and reduces bipolar degradation by suppressing pn or pin diode current with MOS channel assistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device geometries are shrunk to increase device functionalities per unit area, then cost is reduced and functionality per unit area is improved, but reliability requirements become harder to comply with
Solution Approach 1:
The semiconductor device is divided into distinct functional areas: a transistor cell area for active switching, an edge termination area for voltage blocking, and a gate line area for control. This segmentation allows each area to be optimized independently for its specific function while maintaining overall device reliability despite miniaturization.
Solution Approach 2:
Different regions of the device are assigned different structural characteristics: the transistor cell area uses standard MOSFET/IGBT cell structures, the edge termination area employs specialized termination structures (such as junction termination extensions or guard rings), and the gate line area incorporates specific gate electrode configurations. This local differentiation ensures that reliability requirements are met in each specific region without compromising overall device functionality.
2Power
If edge termination area design is optimized to improve current distribution, then surge current capability is enhanced, but device area increases
Solution Approach 1:
The gate line area is positioned to serve dual purposes: it provides gate control for the transistor cells while simultaneously acting as part of the current distribution network during surge conditions. The source/emitter line area similarly combines current carrying function with structural support, reducing the need for separate dedicated surge current paths and minimizing overall device area.
Solution Approach 2:
The edge termination structure is designed to perform multiple functions: it provides voltage blocking capability, establishes uniform current distribution during normal operation, and enhances surge current handling. By integrating these functions into a single structural element rather than using separate components, the device achieves improved surge capability without proportionally increasing area.
3Loss of energy
If transistor cells are added to the source or emitter line area, then on-state resistance is reduced, but device complexity increases
Solution Approach 1:
The source/emitter line area is designed to serve dual purposes: it provides the necessary source/emitter connections for the transistor cells while simultaneously functioning as additional current-carrying path that reduces on-state resistance. By making this area multi-functional rather than adding separate components, the device reduces energy loss without proportionally increasing complexity.
Solution Approach 2:
The source/emitter line area is configured to establish equipotential regions that minimize voltage drops during current flow. By creating multiple parallel current paths through the strategic placement of transistor cells in the source/emitter line area, the device reduces overall on-state resistance while maintaining a relatively simple structural configuration.
Data Source
AI summary
A vertical power semiconductor device includes a semiconductor body having first and second opposite surfaces. A subdivision of an area of the semiconductor body at the first surface includes: a transistor cell area having transistor cells in the semiconductor body; an edge termination area surrounding the transistor cell area, the semiconductor body including a termination structure in the edge termination area; a gate line area between the transistor cell area and the edge termination area, the gate line area including a gate line over the semiconductor body; and a source or emitter line area between the gate line area and the edge termination area. The source or emitter line area includes transistor cells in the semiconductor body, and a source or emitter line over the semiconductor body.