Vertical Power Transistor Layout with Variable Channel Width
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for designing vertical power transistors are cumbersome and require significant effort to adjust parameters like gate drain capacity and channel width, necessitating separate measurements and descriptions for each transistor, which complicates the optimization of circuit speed and volume resistance.
Innovation Solution
A process for designing and simulating vertical power transistors that involves dividing the transistor into partial design pieces with varying gate dielectric lengths, allowing for efficient calculation and adjustment of channel width and gate drain capacity, thereby simplifying the design and reducing the need for extensive parameter measurements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional methods are used to design vertical power transistors, then each transistor requires separate measurements and descriptions, but this makes the design process cumbersome and time-consuming
Solution Approach 1:
The transistor design is divided into modular building blocks (cell designs) that can be independently characterized and then combined. Each cell design represents a standardized unit with defined electrical parameters, allowing designers to assemble complex transistors from these basic units without performing complete separate measurements on each configuration.
Solution Approach 2:
Electrical parameters are pre-calculated and stored for each cell design before actual transistor assembly. This preliminary characterization allows rapid determination of overall transistor parameters through computational combination rather than physical measurement, significantly reducing design time.
2Adaptability or versatility
If the number of individual transistor cells is increased to adjust channel width, then the channel width changes, but this also changes the volume resistance and requires re-measurement
Solution Approach 1:
The invention enables parameter adjustment through mathematical relationships rather than physical redesign. By storing electrical parameters for different cell configurations and using calculation methods, designers can determine the effects of changing cell numbers on channel width and volume resistance without actually building and measuring each variant.
3Measurement precision
If separate measurements are performed for each transistor configuration, then accurate electrical parameters are obtained, but this significantly increases the time and cost of the design process
Solution Approach 1:
Instead of performing physical measurements on each transistor configuration, the invention uses computational models that copy and combine the electrical characteristics of basic cell designs. This virtual characterization approach maintains accuracy while eliminating the time-consuming physical measurement process for each configuration.
Data Source
AI summary
The invention relates to a simulation and/or layout process for vertical power transistors as DMOS or IGBT with variable channel width and variable gate drain capacity which can be drawn and/or designed by the designer with the respectively desired parameters of channel width and gate drain capacity and the parameters of volume resistance and circuit speed, which are correlated therewith, and whose electrical parameters can be described as a function of the geometrical gate electrode design. Here, both discrete and integrated vertical transistors may be concerned.