Vertical Pre-fetch Random Data Buffer for Multi-core Latency
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Solution Overview
Problem
In multi-core processors, existing Random Number Generator (RNG) hardware generates random data with increased latency due to serialized PIO accesses, leading to unfair bandwidth allocation among cores, especially when multiple cores require random data simultaneously.
Innovation Solution
A vertical pre-fetch random data buffer structure is implemented, comprising first, second, and third level buffers, allowing constant generation and dynamic distribution of random data, reducing latency and increasing throughput by enabling cores to fetch data directly from pre-fetch buffers rather than triggering PIO accesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If PIO accesses are used to fetch random data from RNG hardware, then random data can be obtained, but latency increases and bandwidth allocation becomes unfair among cores
Solution Approach 1:
The patent implements a pre-fetch buffer that continuously generates and stores random data before it is actually needed by the cores. This preliminary action eliminates the need for cores to wait for RNG hardware when random data is required, as the data is already available in the pre-fetch buffer, thereby reducing latency while maintaining high bandwidth allocation.
2Ease of operation
If multiple cores simultaneously request random data through serialized PIO accesses, then random data can be fetched, but bandwidth allocation becomes unfair and latency increases
Solution Approach 1:
The patent divides the single RNG hardware resource into multiple independent pre-fetch buffers, one for each core. This segmentation allows each core to have its own dedicated buffer that is independently populated with random data, eliminating the serialization problem when multiple cores simultaneously request random data. Each core can fetch data from its own buffer without waiting for other cores, ensuring fair bandwidth allocation and reduced latency.
3Productivity
If RNG hardware generates random data only after a request is made, then data generation is on-demand, but latency increases
Solution Approach 1:
The pre-fetch buffer continuously generates and accumulates random data in advance, maintaining a ready supply of data. This preliminary generation of random data ensures that when cores need random data, it is already available in the buffer, thereby increasing throughput while minimizing the latency that would otherwise occur if data generation waited for requests.
Data Source
AI summary
Systems and methods for use in enhancing and dynamically allocating random data bandwidth among requesting cores in multi-core processors to reduce system latencies and increase system performance. In one arrangement, a multicore processor includes a vertical pre-fetch random data buffer structure that stores random data being continuously generated by a random data generator (RNG) so that such random data is ready for consumption upon request from one or more of a plurality of processing cores of the multicore processor. Random data received at one data buffer from a higher level buffer may be automatically deposited into the lower level buffer if room exists in the lower level buffer. Requesting strands of a core may fetch random data directly from its corresponding first level pre-fetch buffer on demand rather than having to trigger a PIO access or the like to fetch random data from the RNG.