Vertical Rear Power Structure for Low-Resistance Semiconductor Power Delivery
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Solution Overview
Problem
As demand for high performance, high speed, and multifunctionality in semiconductor devices increases, existing semiconductor devices face challenges in achieving efficient power transfer from the rear surface, leading to limitations in integration density and electrical properties.
Innovation Solution
The semiconductor device incorporates a substrate with an active region, a gate structure, source/drain region, and a vertical power structure connected to a rear power structure, which surrounds the lower and side surfaces of the vertical power structure, enhancing electrical connectivity and reducing resistance through a specific layering and barrier configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If power rails are disposed on the rear surface of the wafer to achieve back side power delivery, then power transfer efficiency is improved, but resistance increases and electrical properties deteriorate
Solution Approach 1:
The patent transitions from conventional planar power delivery to three-dimensional vertical power structures. Power structures extend vertically through multiple layers including the substrate, device isolation layer, and interlayer insulating layer, enabling power delivery in the depth dimension rather than only in the planar surface dimension. This vertical arrangement reduces resistance by providing shorter current paths while maintaining efficient power transfer.
Solution Approach 2:
The patent implements nested power structures where vertical power structures are surrounded by rear power structures that extend along the lower and side surfaces. This nested configuration creates multiple conductive paths in concentric arrangements, reducing overall resistance while maintaining compact integration. The inner vertical power structure is nested within the outer rear power structure, forming a multi-layered conductive system.
2Productivity
If integration density is increased to meet high performance demands, then device functionality is improved, but power transfer efficiency from the rear surface deteriorates
Solution Approach 1:
The patent uses vertical power structures that extend through the substrate and insulating layers to deliver power in the depth dimension. This three-dimensional power delivery approach maintains efficient power transfer even as devices are densely integrated in the planar dimension, because the vertical structures provide dedicated power paths that do not interfere with the increased device density on the surface.
Solution Approach 2:
The patent divides the power delivery system into separate vertical power structures for different devices, with each structure independently extending from the rear surface to the active region. This segmentation allows each device to have its own optimized power path, maintaining efficient power transfer even when multiple devices are densely packed together in the planar direction.
3Reliability
If vertical power structures are implemented to improve power transfer, then resistance is reduced, but device complexity increases
Solution Approach 1:
The patent designs vertical power structures and rear power structures that serve multiple functions: they provide electrical power delivery, act as structural support through the insulating layers, and define regions for device isolation. This multi-functionality reduces the need for separate dedicated components, thereby reducing overall device complexity despite the three-dimensional configuration.
Solution Approach 2:
The patent merges the vertical power structures with the rear power structures into an integrated power delivery system. The vertical structures connect to the rear structures, combining their functions into a unified power network that delivers power from the rear surface through the substrate to the active regions. This merging reduces the number of separate components and simplifies the overall device architecture.
Data Source
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AI summary
A semiconductor device may include an active region extending in a first direction; a gate structure extending in a second direction on the active region; a source/drain region on the active region and disposed at least one side of the gate structure; a contact structure on the source/drain region; a device isolation layer surrounding the active region; an interlayer insulating layer on the device isolation layer, the gate structure, and the source/drain region; a vertical power structure penetrating through the device isolation and interlayer insulating layers and connected to the contact structure; a rear power structure electrically connected to the vertical power structure and surrounding an entirety of a lower surface and a portion of a side surface of the vertical power structure; a vertical insulating film between the vertical power structure and the rear power structure; and a rear insulating film covering a side of the rear power structure.