Vertical Rear Power Structure for Low-Resistance Semiconductor Layouts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As demand for high-performance, high-speed, and multifunctional semiconductor devices increases, existing semiconductor devices face challenges in achieving efficient power transfer and integration density, particularly with the back side power delivery network (BSPDN) structure, where power rails on the rear surface of a wafer do not effectively address resistance issues.
Innovation Solution
The semiconductor device incorporates a vertical power structure connected to a rear power structure that surrounds the lower surface and a portion of the side surface of the vertical power structure, with a conductive barrier and insulating films to enhance electrical connectivity and reduce resistance, while the rear power structure overlaps the vertical power structure in both directions, improving power transfer efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If power rails are disposed on the rear surface of the wafer in a BSPDN structure, then integration density is improved, but resistance issues are not effectively addressed
Solution Approach 1:
The patent transitions from planar power delivery to three-dimensional vertical power delivery by forming vertical power structures that extend through the substrate thickness. This dimensional change allows power to be delivered both horizontally through rear power structures and vertically through contact structures, effectively reducing resistance while maintaining high integration density.
Solution Approach 2:
The patent implements nested power structures where vertical power structures are positioned within and connected to rear power structures. The contact structures extend from the rear surface through the substrate, nested within the vertical regions, creating a multi-level power delivery network that addresses resistance issues while preserving integration density.
2Productivity
If integration density is increased to meet high-performance demands, then device functionality is improved, but power transfer efficiency deteriorates
Solution Approach 1:
The patent introduces vertical power structures extending through the substrate thickness, adding a vertical dimension to power delivery. This three-dimensional approach reduces current path length and resistance, improving power transfer efficiency while supporting high integration density required for advanced device functionality.
Solution Approach 2:
The patent segments the power delivery network into multiple components: rear power structures on the rear surface, vertical power structures extending through the substrate, and contact structures connecting to front surface contacts. This segmentation allows optimized power delivery paths that reduce energy loss while maintaining high integration density.
Data Source
AI summary
A semiconductor device may include an active region extending in a first direction; a gate structure extending in a second direction on the active region; a source/drain region on the active region and disposed at least one side of the gate structure; a contact structure on the source/drain region; a device isolation layer surrounding the active region; an interlayer insulating layer on the device isolation layer, the gate structure, and the source/drain region; a vertical power structure penetrating through the device isolation and interlayer insulating layers and connected to the contact structure; a rear power structure electrically connected to the vertical power structure and surrounding an entirety of a lower surface and a portion of a side surface of the vertical power structure; a vertical insulating film between the vertical power structure and the rear power structure; and a rear insulating film covering a side of the rear power structure.