Vertical Redundancy for 3D Wafer Level Packaged IC Yield
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Solution Overview
Problem
Traditional three-dimensional wafer-level packaging techniques waste valuable wafer area due to spatial correlation between redundant circuits, leading to reduced yield and increased costs, as they require horizontal redundancy on a single substrate, which limits the number of unique circuits that can be fabricated.
Innovation Solution
Implementing a vertical redundancy scheme where active and inactive circuit cells are fabricated on separate wafers, decoupling spatial correlation by bonding opposing circuit cells, with one cell designated as active and the other made inoperable using mini-active and mini-inactive mask plates, allowing for cost-effective use of wafer area without additional selection circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If horizontal redundancy is implemented on a single substrate wafer, then circuit yield is improved through redundancy, but valuable wafer area is wasted and the number of unique circuits that can be fabricated is limited
Solution Approach 1:
The patent transitions from horizontal (planar) redundancy to vertical redundancy by stacking two wafer-level packaged integrated circuits one above the other. The first WLP IC is formed on a first substrate wafer and the second WLP IC is formed on a second substrate wafer, with the wafers bonded together. This vertical stacking allows redundancy to be achieved without consuming additional horizontal wafer area, as each wafer can be fully utilized for unique circuit fabrication.
2Reliability
If horizontal redundancy is implemented on a single substrate wafer, then circuit yield is improved through redundancy, but the number of unique circuits that can be provided on a single wafer is reduced
Solution Approach 1:
By implementing vertical stacking of two independently fabricated WLP ICs, the system achieves circuit redundancy while maintaining full wafer capacity for unique circuit design. Each wafer can be dedicated to a different circuit configuration, thereby increasing the overall number of unique circuits available in the system while the bonded pair provides yield enhancement through redundancy.
Solution Approach 2:
The system divides the redundant circuit functionality into two separate segments fabricated on different wafers. Instead of placing multiple redundant copies of the same circuit on one wafer, the patent segments the redundancy function across two independently fabricated WLP ICs that are then bonded together, allowing each wafer to be optimized for unique circuit designs.
3Ease of manufacture
If planar monolithically processed integrated circuits are used on a common substrate, then fabrication is simplified, but spatial correlation between circuits increases causing reduced effectiveness of redundant backup circuits
Solution Approach 1:
The patent segments the circuit fabrication process into two independent wafer-level packaging processes. Each WLP IC is fabricated, tested, and packaged independently on separate substrate wafers before being bonded together. This segmentation breaks the spatial correlation between circuits that would exist if they were monolithically processed on the same substrate, while still maintaining fabrication efficiency through standardized WLP processes on each wafer.
Solution Approach 2:
The bonding interface between the two substrate wafers acts as an intermediary that connects two independently fabricated and tested WLP ICs. This intermediary connection allows the system to achieve redundancy between spatially uncorrelated circuits while maintaining the ease of manufacture benefits of monolithic WLP fabrication processes on each individual wafer.
Data Source
AI summary
A three-dimensional wafer level packaged (WLP) integrated circuit that includes a pair of opposing circuit cells fabricated on separate wafers that have been bonded together to provide vertical circuit redundancy. The integrated circuits on each of the separate wafers are performance tested prior to the wafers being bonded together so as to designate good performing circuits as active circuit cells and poor performing circuits as inactive circuit cells. The inactive circuit cell for a particular pair of integrated circuits is metalized with a short circuiting metal layer to make it inoperable. The WLP integrated circuit implements a yield-enhancing circuit redundancy scheme on spatially uncorrelated wafers that avoids wasting valuable wafer x-y planar area, which provides cost savings as a result of more wafer area being available for distinct circuits on each wafer rather than sacrificed for traditional side-by-side redundant copies of circuits.